Control & Timers

16-Bit Programmable Prescaler — L1 Upgrade — L2 Upgrade

16-bit programmable prescaler with byte-enable masking, sticky IRQ, and capture logic.

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16-Bit Programmable Prescaler — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 16-bit programmable prescaler designed for high-reliability system timing and event capture. It features byte-level write masking for efficient register updates, a sticky interrupt request (IRQ) mechanism for robust event notification, and a capture logic unit for timestamping or data logging upon timeout events.

The design is fully synchronous with an asynchronous reset, ensuring predictable state transitions. It is suitable for integration into SoCs requiring precise timing control with minimal bus overhead.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Programmable Prescaler — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 16-bit programmable prescaler with byte-enable masking, sticky IRQ, and capture logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Counter: Counts up from zero to a programmable threshold (prescale_val).
Byte-Enable Masking: Allows partial updates of the prescale register via byte_en_h (upper byte) and byte_en_l (lower byte) signals, reducing bus traffic.
Sticky IRQ: Generates a persistent interrupt flag (irq_o) when the counter reaches the prescale value. The flag remains set until explicitly cleared.
IRQ Clear: Supports asynchronous clearing of the IRQ flag via the irq_clear signal.
Capture Logic: Stores a user-defined capture_val into capture_out immediately upon timeout detection, enabling precise event timestamping.
Synchronous Load: The prescale value is loaded into the counter on the rising edge of clk when load is asserted.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	System clock input
`rst_n`	Input	1	Active-low asynchronous reset
`prescale_val`	Input	[15:0]	Prescale threshold value
`capture_val`	Input	[15:0]	Value to capture on timeout
`load`	Input	1	Synchronous load control signal
`byte_en_h`	Input	1	Byte enable mask for upper 8 bits
`byte_en_l`	Input	1	Byte enable mask for lower 8 bits
`irq_clear`	Input	1	Asynchronous clear signal for sticky IRQ
`irq_o`	Output	1	Sticky IRQ output flag
`capture_out`	Output	[15:0]	Captured value output

Verification

The provided testbench (tb_prescaler_16bit_programmable_byte_enable_sticky_irq_capture.v) validates the following scenarios:

Test Case	Description	Result
TC1	Basic Count and Timeout	PASS
TC2	Byte Enable Masking	PASS
TC3	Sticky IRQ Clear	PASS
TC4	Reset Functionality	PASS

### Running Simulation

Ensure your Verilog simulator is installed (e.g., ModelSim, VCS, or Icarus Verilog).
Compile the RTL and testbench files.
Run the simulation.
Check the log output for INFO: PASS to confirm all test cases passed.

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