Control & Timers

8-Channel 16-Bit PWM Controller

Eight-channel 16-bit PWM with global period, per-channel duty, edge/center-aligned modes, and a simplified APB-like register interface.

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About this block

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8-Channel 16-Bit PWM Controller is a SystemVerilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP provides an eight-channel pulse-width modulation generator with 16-bit resolution. It supports global period configuration and independent per-channel duty cycle control. The controller offers both edge-aligned and center-aligned PWM output modes. A simplified APB-like register interface allows easy integration into system buses.

This IP provides a robust and flexible solution for multi-channel PWM generation. It supports high-resolution control with simple register-based configuration. The design is verified through comprehensive testbench scenarios. It is suitable for motor control, LED dimming, and power supply applications.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Channel 16-Bit PWM Controller.
Read the SystemVerilog module in the editor. The catalog line for this block: Eight-channel 16-bit PWM with global period, per-channel duty, edge/center-aligned modes, and a simplified APB-like register interface.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

The module generates eight independent PWM signals from a single clock domain. Each channel supports 16-bit resolution for high-precision control. A global period register sets the frequency for all channels simultaneously. Per-channel duty cycle registers allow individual signal shaping. Edge-aligned mode produces pulses starting from the period zero point. Center-aligned mode produces symmetric pulses around the period midpoint. A global enable signal controls the activation of all PWM outputs. A simplified write-acknowledge interface simplifies register access.

Ports

Port Name	Direction	Width	Description
`clk_i`	Input	1	System clock input
`rst_ni`	Input	1	Active-low asynchronous reset
`cfg_addr_i`	Input	4	Register address for configuration
`cfg_data_i`	Input	16	Data input for register writes
`cfg_wr_i`	Input	1	Write strobe signal
`cfg_ack_o`	Output	1	Acknowledge signal for write operations
`pwm_o`	Output	8	Eight-channel PWM output vector

Architecture

The following diagram illustrates the internal data flow and control logic.

The register file stores the period, duty cycles, and control bits. The counter increments or decrements based on the alignment mode. Comparator logic evaluates the counter against each channel's duty register. The output drivers assert high when the counter is within the duty window.

Verification

The testbench validates reset behavior and register initialization. Period configuration tests verify that the global period updates correctly. Duty cycle configuration tests ensure per-channel values are stored accurately. Channel independence tests confirm that modifying one channel does not affect others. Center-aligned mode tests verify the bidirectional counter operation. Dynamic duty update tests check runtime reconfiguration capabilities. Global enable tests confirm that outputs are suppressed when disabled. All seven test cases passed successfully in the simulation run.

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