Control & Timers
Bang-Bang Thermostat 8-bit
An 8-bit bang-bang thermostat controller with hysteresis for heating control.
About this block
Simulate it in the Verilog IDE
Bang-Bang Thermostat 8-bit is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.
This IP implements a robust bang-bang thermostat controller with 8-bit temperature inputs.
It utilizes hysteresis to prevent rapid switching (oscillation) near threshold boundaries, ensuring stable thermal regulation in embedded systems.
The module asserts heat_out when the input temperature drops below a configurable lower bound and deasserts it when the temperature rises above an upper bound.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Bang-Bang Thermostat 8-bit.
- Read the Verilog module in the editor. The catalog line for this block: An 8-bit bang-bang thermostat controller with hysteresis for heating control.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 8-bit Temperature Comparison: Supports unsigned temperature inputs (0-255).
- Configurable Hysteresis: Independent lower (
temp_lo) and upper (temp_hi) thresholds define the dead band. - Oscillation Prevention: Hysteresis logic ensures the output does not toggle rapidly when temperature fluctuates near thresholds.
- Synchronous Control: Fully synchronous design with active-low reset for clean initialization.
- Verified: Comprehensive testbench covering boundary conditions, hold states, and reset scenarios.
Ports
| Port Name | Direction | Width | Description |
|---|---|---|---|
clk | Input | 1 | System clock input |
rst_n | Input | 1 | Active-low synchronous reset |
temp_in | Input | 8 | Current temperature reading |
temp_lo | Input | 8 | Lower threshold for heating activation |
temp_hi | Input | 8 | Upper threshold for heating deactivation |
heat_out | Output | 1 | Heating control signal (1=ON, 0=OFF) |
Verification
The provided testbench (tb_bang_bang_thermostat_8bit.v) verifies the following scenarios:
| Test Case | Description | Expected Result |
|---|---|---|
| TC1 | Initial state after reset | heat_out = 0 |
| TC2 | Temperature below lower bound | heat_out = 1 |
| TC3 | Hold state from heat | heat_out remains 1 |
| TC4 | Temperature above upper bound | heat_out = 0 |
| TC5 | Hold state from off | heat_out remains 0 |
| TC6 | Rapid transition to heat | heat_out transitions to 1 |
| TC7 | Boundary condition (temp == lo) | heat_out = 1 |
| TC8 | Boundary condition (temp == hi) | heat_out = 1 (Hysteresis hold) |
| TC9 | Inverted check sensitivity | heat_out = 1 |
All 9 test cases passed successfully in Icarus Verilog simulation.
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