Control & Timers

32-Bit Interval Timer with IRQ

A 32-bit down-counter interval timer that generates an interrupt request upon expiration, supporting preload, enable, and acknowledge signals.

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About this block

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32-Bit Interval Timer with IRQ is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This module implements a simple 32-bit down-counter interval timer. It supports loading a preload value, enabling/disabling counting, and generating an interrupt request (IRQ) when the counter expires. The IRQ is cleared upon acknowledgment.

The system consists of a 32-bit counter, a preload register, and an IRQ generation logic. The counter decrements on each clock cycle when enabled. An interrupt is generated when the counter reaches zero. The interrupt is cleared by an acknowledge signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Interval Timer with IRQ.
Read the Verilog module in the editor. The catalog line for this block: A 32-bit down-counter interval timer that generates an interrupt request upon expiration, supporting preload, enable, and acknowledge signals.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`load`	Input	1	Load preload value into counter
`enable`	Input	1	Enable counting (down)
`preload`	Input	32	32-bit preload value
`irq`	Output	1	Interrupt request output (active high)
`irq_ack`	Input	1	Interrupt acknowledge input (active high, pulse)

Verification

The testbench covers reset behavior, counting, IRQ assertion, acknowledgment, and re-triggering. All five test cases pass successfully in the simulation log.

Test Case	Description	Result
TC1	Reset clears IRQ and Counter	PASS
TC2	Count down and IRQ assertion	PASS
TC3	IRQ clear on ACK	PASS
TC4	Reload and count	PASS
TC5	Disable timer	PASS

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