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Control & Timers

1 MHz Tick Generator — L1 Upgrade — L2 Upgrade

Configurable tick generator with sticky interrupt capture and enable control.

Open in IDE Category Wiki · FSM

About this block

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1 MHz Tick Generator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust, configurable tick generator with sticky interrupt handling. It is fully verified against all functional requirements and is ready for integration into larger control systems. The design ensures precise timing intervals and reliable interrupt signaling through its sticky flag mechanism.

The module generates periodic tick signals based on an input clock (clk) and a 16-bit period value (period). It includes a sticky interrupt flag (irq_sticky) that persists until explicitly cleared by the irq_clear signal. This IP is suitable for timing-critical applications requiring precise interval detection and interrupt handling.

This IP provides a robust, configurable tick generator with sticky interrupt handling. It is fully verified against all functional requirements and is ready for integration into larger control systems. The design ensures precise timing intervals and reliable interrupt signaling through its sticky flag mechanism.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 1 MHz Tick Generator — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Configurable tick generator with sticky interrupt capture and enable control.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable Period: 16-bit programmable period value allows for flexible timing intervals.
  • Sticky Interrupt: The irq_sticky flag remains set until cleared, ensuring no interrupt is missed.
  • Synchronous Reset: Active-low synchronous reset for safe initialization.
  • Enable Control: Optional enable signal to pause tick generation without resetting state.

Ports

Port NameDirectionWidthDescription
clkInput1System clock input
rst_nInput1Active-low synchronous reset
enableInput1Enable counter and tick generation (high = active)
irq_clearInput1Active-high clear for sticky IRQ (pulse to clear)
periodInput[15:0]Counter period value for tick generation
tickOutput1Single-cycle pulse when counter matches period
irq_stickyOutput1Sticky interrupt flag set on tick

Verification

The testbench verifies the following functionalities:

  1. Reset behavior (counter and IRQ state).
  2. Tick generation when enabled.
  3. Sticky IRQ capture on tick events.
  4. IRQ clearing via irq_clear signal.
  5. Behavior when disabled (counter holds, no ticks).
  6. Resumption of tick generation after re-enable.
  7. Persistence of sticky IRQ until cleared.
  8. Dynamic period changes.

All eight test cases passed successfully in the simulation log. The simulation was run using Icarus Verilog with a 10ns clock period (100MHz).

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