Control & Timers

16-Bit Down Timer (Match on Load-Zero Too) — L2 Upgrade

A 16-bit down-counter with configurable match value, sticky IRQ generation, and immediate match detection on load-zero.

Open in IDE Category Wiki · FSM

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

16-Bit Down Timer (Match on Load-Zero Too) — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This repository contains the RTL implementation and testbench for a 16-bit down-counter module. The module features match detection, sticky interrupt generation, and immediate trigger capability when loading a zero value. It is designed for scenarios requiring precise timing and event capture, specifically optimized for L2 upgrade integration.

This module implements a 16-bit down-counter with match detection and sticky interrupt generation. It supports loading a preset value and starting the countdown process. The timer triggers a match signal when the counter equals a configurable match value. It also triggers on load-zero, allowing immediate interrupt generation for zero-value loads. The interrupt flag is sticky and must be explicitly cleared via the clear_irq input. This design is suitable for L2 upgrade scenarios requiring precise timing and event capture.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Down Timer (Match on Load-Zero Too) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit down-counter with configurable match value, sticky IRQ generation, and immediate match detection on load-zero.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit Down-Counter: Synchronous load and start controls.
Configurable Match: Set a specific value to trigger interrupts.
Sticky IRQ Flag: Persists until cleared by clear_irq or a new load.
Load-Zero Detection: Immediate match and IRQ generation when loading zero.
Synchronous Reset: Deterministic initialization via rst_n.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`load`	Input	1	Load input value into counter
`start`	Input	1	Start countdown
`clear_irq`	Input	1	Clear sticky IRQ flag
`match_val`	Input	16	Match value for interrupt trigger
`load_val`	Input	16	Value to load into counter
`match`	Output	1	High when counter equals `match_val`
`irq`	Output	1	Sticky interrupt flag

Verification

The testbench verifies four key scenarios:

Test Case	Description	Expected Result
TC1	Basic count down to zero	IRQ and match set when counter reaches 0
TC2	Match value trigger	IRQ and match set when counter equals `match_val`
TC3	Clear IRQ	IRQ flag cleared by `clear_irq` signal
TC4	Load zero match	IRQ and match set immediately on load of zero

All tests passed successfully in the Icarus Verilog simulation environment.

More in Control & Timers

All Control & Timers blocks