Control & Timers

8-Bit Down Timer (Pulse Match on Zero) — L2 Upgrade

An 8-bit down counter with synchronous load, match-zero pulse detection, and a sticky interrupt request flag.

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About this block

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8-Bit Down Timer (Pulse Match on Zero) — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit down counter with synchronous load capability.

It generates a pulse signal (match_zero) when the counter matches zero and asserts a sticky interrupt request (irq_sticky) flag.

The sticky flag can be cleared via an asynchronous reset or a dedicated clear signal.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Down Timer (Pulse Match on Zero) — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit down counter with synchronous load, match-zero pulse detection, and a sticky interrupt request flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Down Counting: Counts down from a loaded value to zero.
Synchronous Load: Supports loading an initial value via load_en.
Match-Zero Detection: Asserts match_zero pulse when the counter reaches zero.
Sticky IRQ: Captures interrupt events with a sticky flag (irq_sticky) to ensure no events are missed.
Asynchronous Reset: Active-low reset (rst_n) for system initialization.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input for synchronous logic.
`rst_n`	Input	1	Active-low asynchronous reset.
`load_val`	Input	8	Data value to load into the counter.
`load_en`	Input	1	Enable signal to load `load_val` into the counter.
`irq_clear`	Input	1	Active-high signal to clear the sticky IRQ flag.
`match_zero`	Output	1	High when the counter value is zero.
`irq_sticky`	Output	1	Sticky flag set on `match_zero`, cleared by `irq_clear`.

Integration

### Instantiation

To integrate this module into your design, use the following Verilog instantiation template:

### Operation Sequence

Initialization: Assert rst_n low to reset the counter to 0. match_zero will be high during reset.
Loading Value: Deassert rst_n. Assert load_en high with load_val set to the desired initial count.
Counting: The counter will decrement on each clock cycle.
Interrupt Handling: When the counter reaches 0, match_zero goes high and irq_sticky is set. Clear irq_sticky by asserting irq_clear high.

Verification

The testbench validates the following scenarios:

Test Case	Description	Result
TC1	Verify `match_zero` is high after reset.	PASS
TC2	Verify `match_zero` is low after loading non-zero value.	PASS
TC3	Verify `match_zero` goes high after counting down to zero.	PASS
TC4	Verify `irq_sticky` is set after match event.	PASS
TC5	Verify `irq_sticky` is cleared by `irq_clear` signal.	PASS
TC6	Verify `match_zero` is high when loading zero value.	PASS
TC7	Verify `irq_sticky` is re-set after loading zero and matching.	PASS

All 7 test cases passed successfully.

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