Control & Timers

16-bit Programmable Timer with Interrupt — L2 Upgrade

A 16-bit down-counter timer with interrupt generation and immediate invalidation support.

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About this block

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16-bit Programmable Timer with Interrupt — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a 16-bit down-counter timer with interrupt generation, designed for L2 upgrade scenarios requiring precise timing.

It supports loading a preset value, counting down to zero, and asserting an interrupt request when the count reaches one.

The timer includes an invalidate signal to clear state immediately, ensuring robust control in dynamic systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-bit Programmable Timer with Interrupt — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A 16-bit down-counter timer with interrupt generation and immediate invalidation support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

16-bit programmable countdown capability.
Asynchronous active-low reset for safe initialization.
Load enable input to update the counter preset value.
Interrupt request output asserted at count value one.
Timer done output synchronized with the interrupt signal.
Invalidate input to clear counter and interrupt flags instantly.
Synchronous logic for predictable timing behavior.
Verified with Icarus Verilog simulation engine.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input for synchronous logic.
rst_n	Input	1	Active-low asynchronous reset.
load_en	Input	1	Load enable to update counter with load_val.
load_val	Input	16	Preset value for the timer counter.
invalidate	Input	1	Active-high signal to clear counter and interrupts.
timer_done	Output	1	High when the timer has reached zero.
interrupt_req	Output	1	High when the counter reaches one.

Verification

The testbench verifies five key scenarios for correctness:

TC1: Basic countdown and interrupt assertion. The counter loads five and counts down to zero correctly.
TC2: Reloading the counter and counting again. The counter loads three and generates an interrupt upon completion.
TC3: Invalidating pending interrupts. The interrupt and timer done signals are reset immediately.
TC4: Interrupt generation after a second reload. The counter loads two and asserts the interrupt request.
TC5: Invalidating before the count completes. The pending interrupt is cleared by the invalidate signal.

All test cases passed with zero errors in simulation.

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