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Control & Timers

Edge Rate Limiter 8-bit — L2 Upgrade

Edge Rate Limiter 8-bit with sticky IRQ capture and configurable threshold.

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About this block

Simulate it in the Verilog IDE

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Edge Rate Limiter 8-bit — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a synchronous edge rate limiter with sticky interrupt request (IRQ) capture.

It counts rising edges on the edge_in signal using an 8-bit counter.

When the count reaches a configurable THRESHOLD, the edge_out signal is asserted.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Edge Rate Limiter 8-bit — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Edge Rate Limiter 8-bit with sticky IRQ capture and configurable threshold.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable Threshold: Adjustable edge count threshold via THRESHOLD parameter.
  • Sticky IRQ Capture: irq_sticky flag persists until explicitly cleared via irq_clear.
  • 8-bit Counter: Supports up to 256 edges before threshold assertion.
  • Synchronous Reset: Clean reset behavior for all internal states via rst_n.
  • Asynchronous Clear: Immediate clearing of the sticky IRQ flag via irq_clear.

Architecture

The module operates on the positive edge of clk. The logic flow is as follows:

  1. Edge Detection: An edge is detected when edge_in transitions from low to high. This is determined by comparing the current edge_in with a delayed version of the internal state (edge_out_d).
  2. Counting: The internal count register increments on each detected edge.
  3. Threshold Check: If count >= THRESHOLD, edge_out is asserted.
  4. IRQ Handling: On any edge detection, irq_sticky is set. It can be cleared by asserting irq_clear.

Interface

Signal NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
edge_inInput1Input signal to monitor for edges
irq_clearInput1Asynchronous clear for sticky IRQ
edge_outOutput1Asserted when edge count >= THRESHOLD
irq_stickyOutput1Sticky flag set on any edge detection

Parameters

ParameterDefaultDescription
THRESHOLD8Edge count threshold to assert edge_out

Verification

The testbench (tb_edge_rate_limiter_8bit_sticky_irq_capture.v) verifies the following scenarios:

  • TC1: Reset state initialization.
  • TC2: Edge counting up to the threshold.
  • TC3: Sticky IRQ clear functionality.
  • TC4: Sustained edge output behavior.
  • TC5: Full reset behavior.

All test cases passed in the provided simulation environment.

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