Control & Timers
Enable-Gated Set/Reset Flag
Enable-Gated Set/Reset Flag with priority clearing and hold state.
About this block
Simulate it in the Verilog IDE
Enable-Gated Set/Reset Flag is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a single-bit registered flag with enable-gated set and clear operations.
It features a priority mechanism where the clear signal takes precedence over the set signal when both are asserted simultaneously.
The flag state is held constant when the enable signal is low, regardless of set/clear inputs.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Enable-Gated Set/Reset Flag.
- Read the Verilog module in the editor. The catalog line for this block: Enable-Gated Set/Reset Flag with priority clearing and hold state.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- Enable Gating: State updates (set/clear) only occur when
enis high. - Priority Clear: If both
setandclrare high, the flag is cleared. - Asynchronous Reset: The flag initializes to
0onrst_nassertion. - Hold State: When
enis low, the flag retains its previous value. - Fully Verified: Includes a comprehensive testbench covering all operational modes.
Architecture
The design utilizes a single D-type flip-flop for state storage. The logic is synchronous to the rising edge of clk but includes an asynchronous reset path.
- Logic Equation:
- If !rst_n: flag <= 0 - Else if en: - If clr: flag <= 0 - Else if set: flag <= 1 - Else: flag <= flag (Hold) - Else: flag <= flag (Hold)
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| clk | Input | 1 | Clock input (rising edge triggered) |
| rst_n | Input | 1 | Active-low asynchronous reset |
| en | Input | 1 | Enable signal; gates set/clear operations |
| set | Input | 1 | Set command (active high) |
| clr | Input | 1 | Clear command (active high) |
| flag | Output | 1 | Registered flag output |
Verification
The provided testbench (tb_sr_flag_en) verifies the following scenarios:
| Test Case | Description | Expected Result |
|---|---|---|
| TC1 | Reset Initialization | flag becomes 0 |
| TC2 | Set Flag Operation | flag becomes 1 |
| TC3 | Clear Flag Operation | flag becomes 0 |
| TC4 | Hold State with en=0 | flag remains unchanged |
| TC5 | Gated Set with en=0 | flag remains unchanged |
| TC6 | Enable and Set | flag becomes 1 |
| TC7 | Clear Wins Over Set | flag becomes 0 when both set/clear are active |
Run the simulation to verify all test cases pass.
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