Control & Timers

Duty-Cycle Measurement 8-Bit — L2 Upgrade

Measures input signal duty cycle as 8-bit percentage with sticky IRQ threshold comparison.

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Duty-Cycle Measurement 8-Bit — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core measures the duty cycle of a periodic input signal over one complete period. It outputs an 8-bit integer percentage (0-100) representing the high-time ratio. The module features a sticky interrupt request (IRQ) that asserts when the measured duty cycle exceeds a configurable threshold. A busy flag indicates when a measurement cycle is in progress, preventing overlapping starts.

This IP is suitable for clock monitoring, signal integrity checks, and power management applications where duty cycle validation is critical.

Choose Open in IDE. RTL Studio loads the packaged workspace for Duty-Cycle Measurement 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Measures input signal duty cycle as 8-bit percentage with sticky IRQ threshold comparison.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Precision: Outputs duty cycle as an integer percentage (0-100).
Configurable Threshold: 8-bit input allows setting a custom IRQ trigger point (0-100).
Sticky IRQ: Interrupt flag remains asserted until explicitly cleared via clear_irq.
Busy Flag: Prevents new measurements from starting while a cycle is in progress. Asserting start while busy is high is ignored.
Synchronous Control: Supports synchronous reset and enable signals for easy integration.
Full Period Measurement: Measures one full high and low cycle before outputting a result.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`start`	Input	1	Trigger a new measurement cycle (ignored if `busy` is high)
`clear_irq`	Input	1	Clear the sticky IRQ flag
`threshold`	Input	8	IRQ threshold percentage (0-100)
`en`	Input	1	Enable signal for counting. Must be high for measurement to proceed.
`duty_cycle`	Output	8	Measured duty cycle percentage
`irq`	Output	1	Sticky interrupt when `duty_cycle > threshold`
`busy`	Output	1	High during measurement cycle

Architecture

The module uses a finite state machine (FSM) to track high and low periods of the input signal. The FSM transitions through four states: IDLE, HIGH, LOW, and DONE.

Counting: Two 16-bit counters (high_count, low_count) accumulate clock cycles while the input signal is high or low, respectively, provided en is asserted.
Calculation: Upon completion of a period (transition to DONE), the duty cycle is calculated as (high_count * 100) / total_count.
IRQ Logic: The calculated duty cycle is compared against the threshold register. If duty_cycle > threshold, the irq flag is set.

Verification

The testbench validates basic functionality and edge cases. All test cases passed in the simulation log.

Test Case	Description	Result
TC1	Basic 50% duty cycle measurement	PASS
TC2	IRQ assertion for 50% > 20% threshold	PASS
TC3	Sticky IRQ clear functionality	PASS
TC4	No IRQ when 50% <= 60% threshold	PASS
TC5	Busy signal assertion and deassertion	PASS

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