Control & Timers

16-Bit Pulse Width Modulator (PWM) Controller

Glitch-free 16-bit PWM with shadow registers for dynamic period/duty updates, active-high output, and full verification.

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16-Bit Pulse Width Modulator (PWM) Controller is a SystemVerilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a glitch-free, 16-bit pulse width modulator with shadow-register-based updates for dynamic period and duty-cycle reconfiguration.

The PWM generates an active-high output waveform where the output is high when the internal free-running counter is less than the current duty register value, and low otherwise.

It supports runtime updates of both period and duty cycle via request signals, with updates committed at the end of the current period (when the counter wraps to zero) to prevent glitches.

Choose Open in IDE. RTL Studio loads the packaged workspace for 16-Bit Pulse Width Modulator (PWM) Controller.
Read the SystemVerilog module in the editor. The catalog line for this block: Glitch-free 16-bit PWM with shadow registers for dynamic period/duty updates, active-high output, and full verification.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Name	Direction	Type	Width	Description
`clk`	input	logic	1	Clock
`rst_n`	input	logic	1	Active-low asynchronous reset
`period_new`	input	logic [15:0]	16	New period value (shadowed on request)
`duty_new`	input	logic [15:0]	16	New duty value (shadowed on request)
`duty_update_req`	input	logic	1	Assert to latch `duty_new` into shadow
`period_update_req`	input	logic	1	Assert to latch `period_new` into shadow
`pwm_out`	output	logic	1	PWM output signal

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