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Control & Timers

Complementary PWM Dead-Time Inserter — L2 Upgrade

Inserts configurable dead-time between complementary PWM signals and captures rising edges for sticky IRQ generation.

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About this block

Simulate it in the Verilog IDE

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Complementary PWM Dead-Time Inserter — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core inserts configurable dead-time between complementary PWM signals to prevent shoot-through in power electronics applications. It features an 8-bit configurable dead-time counter, a 4-state Finite State Machine (FSM), and a sticky interrupt request (IRQ) mechanism triggered by the rising edge of the input PWM signal.

The design ensures safe switching by forcing outputs low during dead-time periods, guaranteeing non-overlapping waveforms for pwm_out_pos and pwm_out_neg.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Complementary PWM Dead-Time Inserter — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Inserts configurable dead-time between complementary PWM signals and captures rising edges for sticky IRQ generation.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable Dead-Time: Adjust dead-time duration via the DT_VAL parameter (up to 255 clock cycles).
  • Complementary Outputs: Generates pwm_out_pos and pwm_out_neg with guaranteed non-overlapping waveforms.
  • Sticky IRQ: Captures rising edges of the input PWM and latches an interrupt flag until cleared by clear_irq.
  • Robust Reset: Asynchronous reset with a defined idle state to ensure predictable power-up behavior.
  • Standard Compliance: Verilog-2001 compliant syntax for broad synthesis tool compatibility.

Ports

Port NameDirectionWidthDescription
clkInput1System clock input
rst_nInput1Active-low asynchronous reset
pwm_inInput1Input PWM signal
clear_irqInput1Clear sticky IRQ flag
pwm_out_posOutput1Positive PWM output
pwm_out_negOutput1Negative PWM output
irq_stickyOutput1Sticky interrupt flag

Verification

The provided testbench verifies the following:

  1. Dead-Time Insertion: Ensures outputs remain low during the configured dead-time window on both rising and falling edges.
  2. IRQ Capture: Validates that the sticky IRQ is set on rising edges and can be cleared via clear_irq.
  3. Reset Behavior: Confirms that all states and outputs initialize correctly upon assertion of rst_n.

### Simulation Results

Run the simulation to see the following log entries:

  • TC1 Pos low during deadtime PASS
  • TC1 Pos high after deadtime PASS
  • TC1 Neg low during active PASS
  • TC2 IRQ sticky set PASS
  • TC2 IRQ sticky cleared PASS
  • TC3 Outputs low during deadtime neg PASS
  • TC3 Outputs in Idle state PASS
  • TC4 Reset state PASS

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