Control & Timers

32-Bit Kick Watchdog with Configurable Timeout and Reset Pulse

A 32-bit watchdog timer with kick reload, runtime timeout reprogramming, and configurable reset pulse width.

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32-Bit Kick Watchdog with Configurable Timeout and Reset Pulse is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

A kick-style 32-bit watchdog for embedded control blocks that need periodic software refresh. Unlike control.watchdog_timer (start/reload with interrupt or reset mode), this IP uses a kick strobe to reload the countdown, runtime timeout_we reprogramming, and a programmable reset_pulse_width on timeout.

The counter decrements every clock cycle after a kick or timeout write. When it reaches one, reset_out asserts high for the configured pulse width, then returns low. A kick before expiry reloads the counter from the stored timeout register without firing reset.

Use this IP when firmware must periodically kick a watchdog and you need a bounded reset pulse width rather than a level-held reset or interrupt flag. Pair it with a CSR bridge or GPIO bit for kick and memory-mapped timeout registers. For start/reload semantics with interrupt vs reset mode, see Control/watchdog_timer.

Choose Open in IDE. RTL Studio loads the packaged workspace for 32-Bit Kick Watchdog with Configurable Timeout and Reset Pulse.
Read the Verilog module in the editor. The catalog line for this block: A 32-bit watchdog timer with kick reload, runtime timeout reprogramming, and configurable reset pulse width.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Name	Direction	Type	Width	Description
`clk`	input	wire	1	System clock
`rst_n`	input	wire	1	Active-low asynchronous reset
`kick`	input	wire	1	Reload countdown from `timeout_reg`
`timeout_val`	input	wire	32	New timeout value (cycles)
`timeout_we`	input	wire	1	Write `timeout_val` and reload counter
`reset_pulse_width_val`	input	wire	32	Reset pulse length in cycles
`reset_pulse_width_we`	input	wire	1	Write reset pulse width register
`reset_out`	output	reg	1	Active-high reset pulse on timeout

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