Control & Timers

Gated Frequency Counter 8-Bit — L2 Upgrade

An 8-bit gated frequency counter supporting binary and Gray code parallel loading with IRQ generation on overflow.

Open in IDE Category Wiki · FSM

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Gated Frequency Counter 8-Bit — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit gated frequency counter with binary or Gray code loading capabilities.

It supports asynchronous reset and generates an interrupt request (IRQ) upon reaching the maximum count value (0xFF).

The module is suitable for L2 difficulty level design projects and includes comprehensive verification via a testbench.

Choose Open in IDE. RTL Studio loads the packaged workspace for Gated Frequency Counter 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit gated frequency counter supporting binary and Gray code parallel loading with IRQ generation on overflow.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-Bit Counting: Counts from 0x00 to 0xFF.
Gated Operation: Counts only when the gate signal is active.
Parallel Load: Supports loading a specific value via load_en.
Gray Code Support: Can interpret load_data as Gray code or binary via gray_load.
Interrupt Request: Asserts irq high when the counter reaches 0xFF.
Asynchronous Reset: Resets counter to 0x00 asynchronously.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`gate`	Input	1	Count enable signal
`load_en`	Input	1	Parallel load enable signal
`load_data`	Input	8	Data to load into the counter
`gray_load`	Input	1	Selects Gray code interpretation for `load_data`
`count_out`	Output	8	Current counter value
`irq`	Output	1	Interrupt request when count reaches 0xFF

Verification

The testbench validates reset behavior, counting, stopping, binary loading, Gray code loading, and IRQ generation. All six test cases passed successfully during simulation.

Test Case	Description	Result
TC1	Reset initialization to 0x00	PASS
TC2	Increment count with gate active	PASS
TC3	Stop counting when gate is inactive	PASS
TC4	Load binary data 0x55	PASS
TC5	Load Gray code 0x0A (interpreted as 0x0C)	PASS
TC6	IRQ assertion at count 0xFF	PASS

To verify the design:

Run the simulation script provided in the sim/ directory.
Check the Log panel for INFO: PASS.
Use the RtlStudio Waveform tab to inspect simulation results via sim/dump.vcd.

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