Control & Timers

Period-Based Frequency Meter 8-Bit — L2 Upgrade

An 8-bit period-based frequency meter that captures clock cycles between rising edges of an input signal. It features a sticky interrupt flag and a synchronous clear mechanism. The counter saturates at 255 to handle long periods.

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About this block

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Period-Based Frequency Meter 8-Bit — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a period-based frequency meter using an 8-bit counter.

It measures the number of clock cycles between rising edges of an input signal (sig_in).

The design features a sticky interrupt flag (irq_sticky) to notify the processor of new period captures and a synchronous clear signal for system synchronization.

Choose Open in IDE. RTL Studio loads the packaged workspace for Period-Based Frequency Meter 8-Bit — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit period-based frequency meter that captures clock cycles between rising edges of an input signal. It features a sticky interrupt flag and a synchronous clear mechanism. The counter saturates at 255 to handle long periods.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Resolution: Measures periods from 1 to 255 clock cycles.
Rising-Edge Detection: Automatically detects transitions on the input signal.
Sticky Interrupt: Asserts irq_sticky on every period capture; requires software clear.
Synchronous Clear: Resets internal state and outputs without affecting the clock domain.
Overflow Protection: Counter saturates at 255 to handle long periods gracefully.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`clear`	Input	1	Synchronous clear signal
`sig_in`	Input	1	Input signal to measure
`period_count`	Output	8	Captured period count (cycles)
`irq_sticky`	Output	1	Sticky interrupt flag (set on capture, cleared by `clear`)

Verification

The design has been verified using Icarus Verilog. The testbench covers the following scenarios:

Test Case	Description	Expected Result
TC1	Reset Test	All outputs zero
TC2	Basic Period Capture	`period_count` equals cycle count
TC3	IRQ Clear	`irq_sticky` and `period_count` clear
TC4	Second Period Capture	New period captured correctly
TC5	Saturation Test	`period_count` saturates at 255
TC6	Reset During Operation	State resets immediately

### Running Simulations

To reproduce the results:

Ensure Icarus Verilog is installed.
Run the simulation script:
Check the log output for:

- TC1 PASS through TC6 PASS - INFO: PASS

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