Control & Timers

Hysteresis Schmitt 8-bit — L1 Upgrade — L2 Upgrade

8-bit Schmitt trigger with sticky interrupt capture and configurable hysteresis thresholds.

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About this block

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Hysteresis Schmitt 8-bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit Schmitt trigger with a sticky interrupt capture mechanism. It detects transitions across defined hysteresis thresholds, captures the input data value at the exact moment of transition, and asserts a sticky interrupt flag (irq_o) on any valid transition. The module supports both asynchronous reset and synchronous clear operations.

This IP provides robust edge detection with noise immunity via hysteresis. It is suitable for sensor interface and signal conditioning applications. The sticky IRQ ensures no transition events are missed, and the captured data allows for precise event logging.

Choose Open in IDE. RTL Studio loads the packaged workspace for Hysteresis Schmitt 8-bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit Schmitt trigger with sticky interrupt capture and configurable hysteresis thresholds.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Parallel Data Input: Processes an 8-bit wide data stream.
Configurable Hysteresis: Upper (THRESH_HIGH) and lower (THRESH_LOW) thresholds are configurable via parameters.
Sticky IRQ Assertion: Asserts an interrupt on both rising and falling edge transitions. The flag remains asserted until explicitly cleared.
Data Capture: Captures the input data value (capture_data) at the exact moment of transition.
Synchronous Clear: Allows explicit clearing of the IRQ flag via clear_n.
Asynchronous Reset: Active-low rst_n resets all internal state.
Verilog-2001 Compatible: Source code is compatible with standard Verilog-2001 simulators.
Simulation Support: Verified with Icarus Verilog.

Architecture

The module uses a single-bit state register to track the current logic level:

High (1): When the input exceeds the upper threshold (THRESH_HIGH).
Low (0): When the input falls below the lower threshold (THRESH_LOW).

Transitions between states trigger the interrupt (irq_o) and data capture (capture_data). The capture register holds the last transition value until reset. The IRQ flag remains asserted until explicitly cleared by clear_n or reset by rst_n.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Asynchronous active-low reset
`data_in`	Input	8	8-bit input data stream
`clear_n`	Input	1	Synchronous active-low IRQ clear
`irq_o`	Output	1	Sticky interrupt output
`capture_data`	Output	8	Captured data at transition

Parameters

Parameter	Default	Description
`THRESH_HIGH`	180	Upper threshold for Low-to-High transition
`THRESH_LOW`	80	Lower threshold for High-to-Low transition

Verification

The testbench (tb_hysteresis_schmitt.v) verifies reset behavior, transition detection, and clear functionality. It checks IRQ assertion and data capture accuracy for both rising and falling edges. It confirms that the IRQ remains sticky until cleared and validates state retention when inputs stay within the hysteresis band.

### Running Simulation

To run the simulation using Icarus Verilog:

### Expected Results

TC1 PASS irq_o is 0 after reset
TC1 PASS capture_data is 0 after reset
TC2 PASS irq_o is 1 after rising edge
TC2 PASS capture_data is 200 after rising edge
TC3 PASS irq_o is 1 after falling edge
TC3 PASS capture_data is 50 after falling edge
TC4 PASS irq_o is 0 after clear
TC5 PASS irq_o is 1 after second rising edge

Test Case	Description	Result
TC1	Reset check	PASS
TC2	Rising Edge Capture	PASS
TC3	Falling Edge Capture	PASS
TC4	Clear IRQ	PASS
TC5	Second Rising Edge	PASS
TC6	Second Falling Edge	PASS
TC7	Second Clear	PASS
TC8	Stay in Low State	PASS
TC9	Transition to High State	PASS
TC10	Transition to Low State	PASS

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