Control & Timers

Linear Ramp Generator 8-bit — L1 Upgrade — L2 Upgrade

An 8-bit linear ramp generator with byte-enable control and sticky IRQ capture upon reaching 0xFF.

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Linear Ramp Generator 8-bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit linear ramp generator designed for precise timing and signal generation applications.

It features configurable step increments, byte-enable gating for selective updates, and a sticky interrupt mechanism to capture completion events.

The design is fully verified via Icarus Verilog simulation and is ready for synthesis in standard digital flows.

Byte-Enable Control: Allows selective updating of the ramp counter based on an 8-bit mask.
Sticky Interrupt: Asserts an irq signal when the ramp reaches 0xFF, which can be cleared asynchronously via irq_clr.
Completion Flag: A done signal indicates when the ramp sequence has finished.
Reset Logic: Asynchronous active-low reset (rst_n) clears all internal states.

Choose Open in IDE. RTL Studio loads the packaged workspace for Linear Ramp Generator 8-bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: An 8-bit linear ramp generator with byte-enable control and sticky IRQ capture upon reaching 0xFF.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Data Width: 8-bit output.
Configurable Step: step_val [7:0] defines the increment amount per clock cycle.
Byte-Enable Mask: byte_en [7:0] gates the ramp progression. If byte_en is 0x00, the counter holds its value.
Sticky IRQ: irq output asserts high when data_out reaches 0xFF and remains high until cleared by irq_clr.
Reset: Asynchronous reset on rst_n clears state, counter, and outputs.
Synchronous IRQ Clear: irq_clr clears the sticky interrupt flag synchronously with the clock.
Done Signal: done asserts high for one cycle when the ramp completes.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`start`	Input	1	Start ramp generation (pulse or level)
`byte_en`	Input	8	Byte enable mask. If `0x00`, counter holds.
`step_val`	Input	8	Increment value for each ramp step
`irq_clr`	Input	1	Synchronous clear for sticky IRQ flag
`data_out`	Output	8	Current ramp counter value
`irq`	Output	1	Sticky interrupt flag (high when ramp completes)
`done`	Output	1	Ramp completion flag (high for 1 cycle)

Verification

The IP has been verified using Icarus Verilog. The testbench covers the following scenarios:

Test Case	Description	Status
TC1	Basic Ramp Generation (step=1)	PASS
TC2	Sticky IRQ Clear Functionality	PASS
TC3	Asynchronous Reset Behavior	PASS
TC4	Byte Enable MSB Handling	PASS
TC5	No Byte Enable (Hold State)	PASS

Running Simulation:

Expected Output:

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