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Control & Timers

Missing Pulse Detector — L2 Upgrade

Detects absence of pulses within a defined window and latches a sticky IRQ flag.

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About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Missing Pulse Detector — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a Missing Pulse Detector with Sticky IRQ Capture. It monitors an input pulse stream and detects the absence of pulses within a defined time window. When a gap between pulses exceeds a configurable threshold, the module asserts a sticky interrupt request (irq_sticky). This flag remains set until explicitly cleared via the irq_clear signal, ensuring that missing pulse events are not lost even if the host processor is busy.

The design is fully synchronous, uses an active-low asynchronous reset, and provides a direct pulse_detected output for real-time monitoring.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Missing Pulse Detector — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Detects absence of pulses within a defined window and latches a sticky IRQ flag.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable Detection Window: Set the gap threshold via the GAP_THRESH parameter.
  • Sticky Interrupt: The irq_sticky flag latches the missing pulse event and persists until cleared.
  • Explicit Clear: The sticky IRQ can only be cleared via the irq_clear input signal.
  • Real-time Monitoring: Direct pulse_detected output reflects the current state of pulse_in.
  • Synchronous Design: Fully synchronous logic with active-low asynchronous reset for robust integration.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
pulse_inInput1Input pulse stream
irq_clearInput1Active-high clear for sticky IRQ
pulse_detectedOutput1High when pulse_in is high
irq_stickyOutput1Sticky interrupt flag

Architecture

The module consists of two main logic blocks:

  1. Gap Counter: An 8-bit counter increments on every clock cycle when pulse_in is low. If pulse_in goes high, the counter resets to zero. If the counter exceeds the GAP_THRESH parameter, a missing_pulse_flag is asserted.
  2. Sticky IRQ Latch: This block latches the missing_pulse_flag into the irq_sticky output. The latch is only cleared when irq_clear is asserted or when rst_n is de-asserted.

Verification

The provided testbench (tb_missing_pulse_detector_sticky_irq_capture.v) validates the following scenarios:

Test CaseDescriptionResult
TC1Reset behavior checkPASS
TC2Normal pulse stream (no missing pulse)PASS
TC3Missing pulse detection and sticky IRQPASS
TC4IRQ clear functionalityPASS
TC5Pulse detection output high/lowPASS

### Running Simulation

To verify the design, run the simulation using your preferred Verilog simulator. For example, using Icarus Verilog and GTKWave:

Upon successful completion, the log should display:

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