Control & Timers

Non-Retriggerable One-Shot — L2 Upgrade

Non-retriggerable one-shot pulse generator with sticky IRQ capture and configurable pulse width.

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Non-Retriggerable One-Shot — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a non-retriggerable one-shot pulse generator with a sticky interrupt request (IRQ) flag. It generates a fixed-width output pulse upon a trigger event. Subsequent triggers during the active pulse are ignored. A sticky interrupt flag is set when the pulse completes and persists until explicitly cleared via an asynchronous clear signal.

This module is suitable for event capture, debouncing, and simple interrupt notification systems where pulse integrity is critical.

The oneshot_non_retriggerable_sticky_irq_capture module provides a robust solution for generating single-cycle or multi-cycle pulses that cannot be re-triggered while active. Key behaviors include:

Non-Retriggerable: Once triggered, the module ignores further trigger inputs until the pulse completes.
Sticky IRQ: An interrupt flag is asserted when the pulse finishes and remains asserted until cleared.
Asynchronous Clear: The sticky IRQ flag can be cleared asynchronously via the clear_irq signal.
Configurable Width: The pulse width is determined by the PULSE_WIDTH parameter (default: 4 cycles).

Choose Open in IDE. RTL Studio loads the packaged workspace for Non-Retriggerable One-Shot — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Non-retriggerable one-shot pulse generator with sticky IRQ capture and configurable pulse width.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Non-retriggerable behavior ensures a single pulse per trigger event.
Sticky IRQ flag persists until explicitly cleared.
Asynchronous reset (rst_n) for reliable initialization.
Simple synchronous control interface.
Parameterizable pulse width (PULSE_WIDTH).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`trigger_in`	Input	1	Trigger pulse to start one-shot (synchronous detection)
`clear_irq`	Input	1	Active-high clear for sticky IRQ (asynchronous)
`pulse_out`	Output	1	Active-high pulse during one-shot
`irq_sticky`	Output	1	Sticky interrupt flag

Verification

The testbench (tb_oneshot_non_retriggerable_sticky_irq_capture.v) verifies the following scenarios:

Test Case	Description
TC1	Basic Trigger and Pulse Generation
TC2	Non-Retriggerable Behavior
TC3	Sticky IRQ Clear Functionality
TC4	Trigger after Clear

### Running Simulation

To run the simulation using Icarus Verilog:

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