Control & Timers

Retriggerable One-Shot — L2 Upgrade

A retriggerable one-shot pulse generator with configurable width and sticky interrupt capture.

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Retriggerable One-Shot — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a retriggerable one-shot pulse generator with a sticky interrupt flag. It generates a pulse of configurable width upon trigger. If a new trigger arrives while the pulse is active, the timer resets, extending the pulse duration. A sticky interrupt flag (irq_sticky) is asserted when the pulse completes and must be cleared explicitly via the clear_irq signal.

### Key Features

Retriggerable: Extends pulse duration on subsequent triggers by resetting the internal counter.
Configurable Width: 8-bit input for pulse duration in clock cycles (1 to 255).
Sticky Interrupt: Latches high on pulse completion; requires explicit clear via clear_irq.
Robust Reset: Asynchronous active-low reset for initialization.

The module is designed for timing control and event capture applications where precise pulse generation and interrupt notification are required. It uses a synchronous counter to manage the pulse width and retriggering logic. The design ensures that the output pulse remains high as long as the trigger is active or the counter is running.

Choose Open in IDE. RTL Studio loads the packaged workspace for Retriggerable One-Shot — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A retriggerable one-shot pulse generator with configurable width and sticky interrupt capture.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock signal
`rst_n`	Input	1	Active-low asynchronous reset
`trigger_in`	Input	1	Trigger signal to start or retrigger the pulse
`clear_irq`	Input	1	Synchronous clear for the sticky IRQ flag
`pulse_width`	Input	8	Width of the output pulse in clock cycles
`pulse_out`	Output	1	Generated pulse signal
`irq_sticky`	Output	1	Sticky interrupt flag set on pulse completion

Architecture

The design utilizes a counter that increments when triggered. The counter resets to zero upon reaching the configured pulse_width or when a new trigger is received (retriggering).

Count Enable: Active when trigger_in is high or the counter is running (counter > 0), and the terminal count is not reached.
Terminal Count: Detected when counter == pulse_width.
Pulse Output: High while the counter is running (trigger_active is true). The pulse is set on trigger and cleared on terminal count.
Sticky IRQ: Latched high when the terminal count is reached. Cleared synchronously by clear_irq.

### Logic Flow

Trigger: When trigger_in goes high, trigger_active becomes true, enabling the counter.
Counting: The counter increments every clock cycle while count_enable is true.
Retrigger: If trigger_in goes high again while counting, the counter resets to 0, extending the pulse.
Completion: When counter == pulse_width, count_terminal is asserted. The pulse output goes low, and irq_sticky is latched high.
Clear IRQ: The user must assert clear_irq to reset irq_sticky to low.

Verification

The testbench verifies the following scenarios:

TC1: Basic one-shot pulse generation.
TC2: Sticky IRQ flag latching and clearing.
TC3: Retriggerable behavior (pulse extension).
TC4: Multiple rapid triggers.

All test cases pass successfully.

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