Control & Timers

One-Shot Timer with Hold — L2 Upgrade

A configurable one-shot timer with hold capability and sticky interrupt capture logic.

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About this block

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One-Shot Timer with Hold — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a synchronous one-shot timer with a configurable width, a hold feature to extend the output pulse, and a sticky interrupt flag.

It is designed for applications requiring precise timing events with reliable interrupt notification.

The design is fully synchronous, resettable, and verified through comprehensive test cases covering triggering, holding, clearing, and re-triggering scenarios.

Configurable Width: 8-bit counter limit.
Hold Functionality: Extends the timer_done pulse as long as hold_in is asserted.
Sticky IRQ: Latches the completion event until explicitly cleared.
Synchronous Reset: Active-low reset for all internal state.

Choose Open in IDE. RTL Studio loads the packaged workspace for One-Shot Timer with Hold — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: A configurable one-shot timer with hold capability and sticky interrupt capture logic.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module consists of three main logic blocks:

Counter Logic: A synchronous counter driven by clk. It resets on rst_n or trigger_in and increments until it reaches timer_width.
Timer Done Logic: Generates the timer_done signal. It is asserted when the counter equals the width and remains asserted if hold_in is high.
Sticky IRQ Logic: Sets the irq_sticky flag when the timer completes. The flag is cleared by the irq_clear signal.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
trigger_in	Input	1	Trigger pulse to start timer
hold_in	Input	1	Hold signal to maintain timer_done
irq_clear	Input	1	Clear sticky IRQ flag
timer_width	Input	8	Counter limit value
timer_done	Output	1	Timer completion signal
irq_sticky	Output	1	Sticky interrupt flag

Verification

The testbench verifies five key scenarios:

TC1: Basic timer triggering and completion.
TC2: Sticky IRQ latching behavior.
TC3: IRQ clear signal functionality.
TC4: Hold functionality during and after assertion.
TC5: Re-triggering capability after clearing.

All tests passed successfully in simulation.

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