Control & Timers

Programmable One-Shot with Rearm Gap — L2 Upgrade

Programmable one-shot pulse generator with rearm gap and sticky IRQ capture.

Open in IDE Category Wiki · FSM

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Programmable One-Shot with Rearm Gap — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a programmable one-shot pulse generator with a rearm gap feature.

It captures a sticky interrupt request (IRQ) upon timeout completion.

The module supports dynamic width configuration via an 8-bit input and allows for early termination of the pulse via a rearm signal, enabling precise gap control between events.

Choose Open in IDE. RTL Studio loads the packaged workspace for Programmable One-Shot with Rearm Gap — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Programmable one-shot pulse generator with rearm gap and sticky IRQ capture.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Programmable Pulse Width: Configurable duration via an 8-bit width input.
Sticky IRQ: Generates a sticky high state on irq_o upon timeout, clearable via irq_clear.
Rearm Gap: The rearm_n signal allows early termination of the pulse and counter reset, enabling precise gap control between events.
Edge Detection: Internal edge detection for trigger_i and rearm_n inputs.
Asynchronous Reset: Global reset via rst_n.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low reset
trigger_i	Input	1	Rising-edge trigger input
rearm_n	Input	1	Active-low rearm input
irq_clear	Input	1	Active-high IRQ clear input
width	Input	8	Pulse width in clock cycles
pulse_o	Output	1	One-shot pulse output
irq_o	Output	1	Sticky IRQ output

Verification

The testbench covers five key scenarios:

TC1: Basic trigger and pulse width accuracy.
TC2: Sticky IRQ capture after timeout.
TC3: Asynchronous IRQ clearing.
TC4: Rearm gap functionality.
TC5: Multiple trigger and rearm sequences.

### Running Simulation

Ensure Icarus Verilog is installed.
Run the simulation script:
Check the Log panel for:

- TC1 PASS through TC5 PASS - INFO: PASS

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