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Control & Timers

Pulse Width Window Checker 8-bit

Measures high-pulse width on din and validates it against min/max thresholds with sticky fail flag.

Open in IDE Category Wiki · FSM

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Pulse Width Window Checker 8-bit is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core validates that the duration of a digital pulse on the din signal falls within a user-defined range (min_pw to max_pw). It is designed for timing-critical control systems where pulse width integrity is essential.

Key Features:

  • Window Validation: Checks if the pulse width (in clock cycles) is between min_pw and max_pw.
  • Sticky Failure Flag: The fail output latches high if any measurement falls outside the window, persisting until reset.
  • Immediate Status: The ok output reflects the validity of the most recent measurement.
  • Configurable Range: Supports 8-bit thresholds for flexible timing windows.

The module measures the number of clock cycles the din signal remains high. The measurement is triggered by the start signal. Once triggered, the module counts cycles while din is high. When din goes low, the counter value is compared against the configured thresholds.

  • Measurement: Counts clock cycles during the high phase of din.
  • Validation: Compares the count against min_pw and max_pw.
  • Status:
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Pulse Width Window Checker 8-bit.
  2. Read the Verilog module in the editor. The catalog line for this block: Measures high-pulse width on din and validates it against min/max thresholds with sticky fail flag.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

PortDirectionWidthDescription
clkinput1System clock
rst_ninput1Active-low asynchronous reset
startinput1Trigger to begin measurement (pulse width >= 1 cycle)
dininput1Signal to measure pulse width
min_pwinput8Minimum acceptable pulse width (cycles)
max_pwinput8Maximum acceptable pulse width (cycles)
okoutput1High if last pulse was in window
failoutput1Sticky flag if any pulse was out of window

Architecture

The module implements a synchronous Finite State Machine (FSM) with three primary states:

  1. Idle: Waiting for the start trigger.
  2. Measuring: Counting cycles while din is high.
  3. Evaluating: Comparing the counter value against thresholds upon the falling edge of din.

### State Diagram

Verification

The provided testbench (tb_pulse_width_window_check_8.v) covers the following scenarios:

  • Reset Behavior: Verifies all outputs are zeroed upon reset.
  • In-Window Pulse: Validates a pulse width within the specified range.
  • Out-of-Window (Short): Validates a pulse width shorter than min_pw.
  • Out-of-Window (Long): Validates a pulse width longer than max_pw.
  • Boundary Conditions: Tests exact equality with min_pw and max_pw.

All test cases are designed to pass, confirming the correctness of the window checking logic.

To run the simulation:

  1. Open your preferred HDL simulator.
  2. Load tb_pulse_width_window_check_8.v.
  3. Run the simulation and check the log for INFO: PASS.

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