Control & Timers

Traffic-Light Controller FSM — L2 Upgrade

Traffic-Light Controller FSM with sticky IRQ capture and emergency override.

Open in IDE Category Wiki · FSM

About this block

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Traffic-Light Controller FSM — L2 Upgrade is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Hard: a larger reference. Simulate the packaged testbench before you change the RTL.

This IP implements a finite state machine (FSM) for a traffic light controller. It is designed for educational purposes and simple embedded traffic control applications.

The design supports configurable timing for Red, Green, and Yellow phases, includes an emergency override input, and features a sticky interrupt flag that asserts during the Yellow state or upon emergency detection.

This IP provides a robust, configurable traffic light controller FSM with emergency handling and interrupt signaling.

Choose Open in IDE. RTL Studio loads the packaged workspace for Traffic-Light Controller FSM — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Traffic-Light Controller FSM with sticky IRQ capture and emergency override.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Timing: Adjust cycle counts for Green, Yellow, and Red phases via parameters.
Emergency Override: Immediate transition to Red state upon assertion of the emergency input.
Sticky Interrupt: irq_o asserts during the Yellow state or on emergency detection and persists until cleared by irq_clear.
Synchronous Reset: Resets to the initial Red state synchronously.
Verilog-2001 Compatible: Standard syntax for broad tool support.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	System clock
`rst_n`	Input	1	Active-low synchronous reset
`start`	Input	1	Start signal to begin Green phase from Red
`emergency`	Input	1	Active-high emergency override to Red
`irq_clear`	Input	1	Active-high signal to clear the sticky IRQ
`state_out`	Output	2	Current state: `00`=Red, `01`=Green, `10`=Yellow
`irq_o`	Output	1	Sticky interrupt flag

Architecture

The design consists of a state register, next-state logic, three independent counters, and an IRQ latch.

State Machine: Transitions through Red, Green, and Yellow based on counter thresholds.
Start Logic: The start signal is required to leave the Red state.
Emergency Logic: Emergency inputs bypass normal timing and force an immediate Red state transition.

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