Control & Timers

Up/Down Limit FSM 8-bit

Saturating up/down counter with fixed 8-bit limits and boundary flags.

Open in IDE Category Wiki · FSM

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

Up/Down Limit FSM 8-bit is a Verilog reference block in the Control & Timers catalog. FSMs, timers, watchdogs, and control/state sequencing blocks. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements a saturating up/down counter with fixed 8-bit limits (0x00 to 0xFF).

It counts up or down based on the direction input while respecting enable gating.

The counter saturates at 0x00 (minimum) and 0xFF (maximum).

Choose Open in IDE. RTL Studio loads the packaged workspace for Up/Down Limit FSM 8-bit.
Read the Verilog module in the editor. The catalog line for this block: Saturating up/down counter with fixed 8-bit limits and boundary flags.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Synchronous Control: Supports synchronous reset and clock enable.
Boundary Detection: Provides status flags for minimum (at_min) and maximum (at_max) count values.
Saturating Logic: Prevents overflow/underflow by holding the value at limits.
8-bit Width: Standard 8-bit counting capability.

Ports

Port	Direction	Width	Description
clk	Input	1	Clock input
rst_n	Input	1	Active-low synchronous reset
en	Input	1	Enable signal (gates counting)
dir	Input	1	Direction control (1: up, 0: down)
count	Output	8	Current counter value
at_min	Output	1	High when count equals 0x00
at_max	Output	1	High when count equals 0xFF

Verification

The provided testbench (tb_up_down_limit_fsm_8bit.v) validates:

Reset behavior (count goes to 0x00).
Counting up to maximum value.
Saturation at maximum value.
Counting down to minimum value.
Saturation at minimum value.
Enable gating and resume functionality.

All six test cases passed successfully in the simulation log.

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