Edge, Debounce & Pulse

Both-Edge Detector — L1 Upgrade

Both-edge detector with N-cycle hold pulse generation.

Open in IDE Category Wiki · edge / FF

About this block

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Both-Edge Detector — L1 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a both-edge detector with a configurable N-cycle hold pulse. It detects rising and falling edges on the input signal in. Upon edge detection, the output pulse remains high for a specified number of clock cycles. The hold duration is controlled by the hold_n input port.

This IP provides a robust solution for detecting signal edges with a configurable pulse width. It is suitable for applications requiring debouncing or pulse stretching. The design is simple, efficient, and fully verified.

Choose Open in IDE. RTL Studio loads the packaged workspace for Both-Edge Detector — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Both-edge detector with N-cycle hold pulse generation.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Both-Edge Detection: Detects both rising and falling edges on the input signal.
Configurable Pulse Width: The hold_n parameter (4-bit width, max 15 cycles) controls the pulse duration.
Synchronous Reset: Active-low synchronous reset (rst_n).
Simple Logic: Efficient synchronous logic implementation using a shift register and counter.
Self-Checking Testbench: Includes a comprehensive testbench with automated pass/fail reporting.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`in`	Input	1	Input signal to monitor for edges
`hold_n`	Input	4	Number of cycles to hold pulse high (0-15)
`pulse`	Output	1	Output pulse signal

Architecture

The module uses a shift register approach to detect edges by comparing the current input with the previous clock cycle's input. A counter decrements when an edge is detected and the pulse is active. The pulse remains high until the counter reaches zero.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Result
TC1	Reset check ensures pulse is low initially.	PASS
TC2	Rising edge detection with hold N=2.	PASS
TC3	Falling edge detection with hold N=2.	PASS
TC4	No edge condition results in no pulse.	PASS
TC5	Hold N=0 results in 1-cycle pulse.	PASS

All tests passed successfully. Simulation logs confirm correct behavior for all edge cases.

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