Edge, Debounce & Pulse

Rising-Edge Event Counter 8-Bit — L1 Upgrade — L2 Upgrade

8-bit rising-edge event counter with load, clear, windowing, and sticky flag support.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Rising-Edge Event Counter 8-Bit — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements an 8-bit rising-edge event counter designed for Level 1 (L1) and Level 2 (L2) upgrade scenarios in high-speed data acquisition systems. It provides precise event tracking with programmable windowing limits, synchronous load/clear capabilities, and a sticky flag for event detection.

The module is fully verified, synthesizable, and ready for integration into larger FPGA designs.

Choose Open in IDE. RTL Studio loads the packaged workspace for Rising-Edge Event Counter 8-Bit — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-bit rising-edge event counter with load, clear, windowing, and sticky flag support.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Counter Width: Accumulates events from 0 to 255.
Rising-Edge Detection: Accurately counts pulses on the pulse_in signal by detecting transitions from 0 to 1.
Synchronous Load: Preloads the counter with data_in when load is asserted.
Synchronous Clear: Resets the counter and sticky flag to zero when clear is asserted.
Enable Control: Gates counting operations via the en signal.
Windowing Logic: Prevents counting beyond a specified threshold (window_val) when window_en is active. The counter holds its value if the limit is reached.
Sticky Flag: Sets to 1 upon the first valid count event and remains high until explicitly cleared by the clear signal.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`en`	Input	1	Count enable signal
`load`	Input	1	Load data input signal
`clear`	Input	1	Clear counter and sticky flag
`data_in`	Input	8	Data input for load operation
`window_en`	Input	1	Window enable signal
`window_val`	Input	8	Window threshold value
`pulse_in`	Input	1	Pulse input for counting
`count_out`	Output	8	Current counter value
`sticky_flag`	Output	1	Sticky flag indicating first count

Architecture

The module utilizes sequential logic for state storage and combinational logic for next-state calculation.

Rising-Edge Detection: Performed by comparing the current pulse_in with the previous cycle's value (prev_pulse).
Priority Logic: The counter updates based on the priority of signals: load > clear > enable.
Windowing: If window_en is active, the counter increments only if count_out < window_val. Otherwise, it holds the current value.
Sticky Flag: Set to one upon the first successful count event and remains high until clear is asserted.

Verification

The testbench verifies reset, basic counting, load, clear, windowing, and sticky flag behavior. All test cases passed successfully in the simulation environment.

Test Case	Description	Result
TC1	Reset functionality	PASS
TC2	Basic counting up to 10	PASS
TC3	Load value 42	PASS
TC4	Clear counter and sticky flag	PASS
TC5	Windowing limit at 5	PASS
TC6	Sticky flag sensitivity	PASS

More in Edge, Debounce & Pulse

All Edge, Debounce & Pulse blocks