Edge, Debounce & Pulse

Falling-Edge Hold for N Cycles — L1 Upgrade

Detects a falling edge on sig_in and asserts sig_out for a configurable number of clock cycles defined by hold_n.

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Falling-Edge Hold for N Cycles — L1 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core detects a falling edge on an input signal (sig_in) and asserts an output pulse (sig_out) for a configurable number of clock cycles.

The duration is determined by the hold_n input vector.

Designed for L1 signal processing upgrades, this module ensures precise pulse widening with robust handling of consecutive edges and asynchronous reset.

Choose Open in IDE. RTL Studio loads the packaged workspace for Falling-Edge Hold for N Cycles — L1 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Detects a falling edge on sig_in and asserts sig_out for a configurable number of clock cycles defined by hold_n.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Hold Duration: Set via an 8-bit hold_n input (0-255 cycles).
Asynchronous Reset: Active-low rst_n clears all internal state and outputs immediately.
Edge Detection: Detects falling edges on sig_in to trigger the hold pulse.
Precise Timing: Outputs a high pulse on sig_out lasting exactly hold_n cycles.
Robustness: Handles multiple consecutive falling edges and rising edges during the hold period correctly.
Zero Hold Support: Supports hold_n = 0 for immediate release after detection (1-cycle pulse).

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input (positive edge triggered)
`rst_n`	Input	1	Asynchronous reset, active low
`hold_n`	Input	8	Number of cycles to hold `sig_out` high (0-255)
`sig_in`	Input	1	Input signal to monitor for falling edge
`sig_out`	Output	1	Output pulse signal

Architecture

The module implements a 4-state finite state machine (FSM) to manage signal transitions safely. The states are IDLE, FALL, HOLD, and RIS.

IDLE: Waits for a falling edge on sig_in.
FALL: Confirms the signal remains low. If confirmed, transitions to HOLD and loads hold_n into the counter.
HOLD: Decrements the counter each cycle. When the counter reaches 1, transitions to RIS.
RIS: A transient state to ensure sig_out is deasserted before returning to IDLE, preventing glitches.

### State Diagram

Verification

The testbench tb_falling_edge_hold_hold_both_n.v verifies the following scenarios:

Test Case	Description	Result
TC1	Basic falling edge detection and hold for N=3	PASS
TC2	Rising edge handling during hold	PASS
TC3	Asynchronous reset behavior	PASS
TC4	Hold N=0 (immediate release)	PASS
TC5	Multiple consecutive falling edges	PASS

All tests passed successfully in the Icarus Verilog simulation.

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