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Edge, Debounce & Pulse

Edge-Triggered Single-Cycle Pulse Generator — L1 Upgrade — L2 Upgrade

Edge-Triggered Single-Cycle Pulse Generator with configurable window width and sticky flag.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

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Edge-Triggered Single-Cycle Pulse Generator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core generates a single pulse of configurable width upon a trigger event.

It supports both rising and falling edge detection (via external logic or input conditioning) and maintains a sticky flag to indicate that a trigger event has occurred.

The module is designed for L1 and L2 upgrade scenarios requiring precise timing control and event tracking.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Edge-Triggered Single-Cycle Pulse Generator — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: Edge-Triggered Single-Cycle Pulse Generator with configurable window width and sticky flag.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Edge-Triggered: Detects trigger events to initiate pulse generation.
  • Configurable Width: Pulse duration is defined by the window_width input (0-15 cycles).
  • Sticky Flag: A status bit (sticky_flag) latches the occurrence of a trigger event.
  • Explicit Clear: The sticky flag can be reset synchronously via clear_sticky.
  • Zero-Width Support: Handles window_width = 0 gracefully (pulse expires immediately).
  • Asynchronous Reset: Supports active-low asynchronous reset for system initialization.

Ports

Port NameDirectionWidthDescription
clkInput1System clock input
rst_nInput1Active-low asynchronous reset
triggerInput1Trigger signal. Pulse generation starts on assertion.
clear_stickyInput1Active-high synchronous clear for sticky_flag
window_widthInput4Pulse width in clock cycles (0-15)
pulse_outOutput1Active-high pulse output
sticky_flagOutput1Latched indicator that a trigger event occurred

Architecture

The module uses a synchronous down-counter to manage the pulse duration.

  1. Sticky Logic: The sticky_flag is set to 1 whenever trigger is asserted. It is cleared to 0 only when clear_sticky is asserted. This logic is independent of the pulse generation state.
  2. Pulse Logic: When trigger is asserted, pulse_active is set to 1 and window_cnt is loaded with window_width.
  3. Counting: On subsequent clock cycles, if pulse_active is high, window_cnt decrements. When window_cnt reaches 0, pulse_active is cleared, ending the pulse.

### Block Diagram

Verification

The provided testbench (tb_pulse_gen_1shot_edge_hold_both_window_sticky.v) covers:

  • Basic triggering with various window widths.
  • Sticky flag setting and clearing.
  • Edge cases (window_width = 0, 1, 15).
  • Reset behavior.

### Running Simulation

  1. Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim).
  2. Run the simulation:
  3. Check the log for INFO: PASS.

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