RTL Studio Open IDE

Edge, Debounce & Pulse

Pulse Width Monitor

Measures the width of an input pulse in clock cycles and latches the result.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Pulse Width Monitor is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The Pulse Width Monitor is a lightweight, synchronous digital IP core designed to measure the duration of an input pulse in clock cycles.

It latches the count upon the falling edge of the input signal and provides a valid flag to indicate when a measurement is complete.

This IP is suitable for timing analysis, pulse detection, and simple event duration monitoring in digital designs.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Pulse Width Monitor.
  2. Read the Verilog module in the editor. The catalog line for this block: Measures the width of an input pulse in clock cycles and latches the result.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Pulse Width Measurement: Measures pulse duration from 1 to 255 clock cycles.
  • Asynchronous Reset: Active-low reset (rst_n) clears all internal states immediately.
  • Valid Flag: Output width_valid asserts for one clock cycle when a measurement is complete.
  • 8-bit Output: Provides the measured width in an 8-bit register (width_count).
  • Synchronous Operation: All logic is synchronous to the rising edge of clk.

Architecture

The module implements a simple finite state machine (FSM) with two states: IDLE and MEASURING.

  1. IDLE State: The counter is zero, and width_valid is low. The module waits for din to go high.
  2. MEASURING State: The counter increments on each clock cycle while din is high. If din goes low, the current count is latched to width_count, width_valid is asserted, and the state returns to IDLE.

### Block Diagram

Ports

Port NameDirectionWidthDescription
clkInput1Clock input (rising edge triggered)
rst_nInput1Active-low asynchronous reset
dinInput1Pulse input signal to measure
width_validOutput1Asserted high for 1 cycle when measurement is complete
width_countOutput8Measured pulse width in clock cycles

Verification

The provided testbench (tb_pulse_width_monitor.v) verifies the following scenarios:

  • Reset Behavior: Ensures all outputs are zero after reset.
  • Single-Cycle Pulse: Verifies correct measurement of a 1-cycle pulse.
  • Multi-Cycle Pulse: Verifies correct measurement of 5-cycle and 10-cycle pulses.
  • Idle State: Ensures width_valid remains low when no pulse is present.

### Running Simulation

  1. Compile the RTL and testbench files.
  2. Run the simulation.
  3. Check the log output for INFO: PASS.

Expected log output:

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