RTL Studio Open IDE

Edge, Debounce & Pulse

Single-Cycle Pulse Generator with Enable Gating — L1 Upgrade — L2 Upgrade

A single-cycle pulse generator that detects both positive and negative edges, gated by an enable signal and constrained by a configurable window duration. Includes a sticky flag for event latching.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Single-Cycle Pulse Generator with Enable Gating — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core generates single-cycle pulses on both positive and negative edges of an input signal.

It features a configurable window duration to control pulse width and enable gating for conditional pulse generation.

A sticky flag records any pulse activity until cleared.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Single-Cycle Pulse Generator with Enable Gating — L1 Upgrade — L2 Upgrade.
  2. Read the Verilog module in the editor. The catalog line for this block: A single-cycle pulse generator that detects both positive and negative edges, gated by an enable signal and constrained by a configurable window duration. Includes a sticky flag for event latching.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Edge Detection: Detects both positive and negative transitions on the input signal.
  • Enable Gating: Output pulses are generated only when the en signal is active.
  • Configurable Window: The win input defines the duration of the output pulse in clock cycles.
  • Sticky Flag: A latched flag (sticky_flag) indicates that a pulse event has occurred, remaining set until cleared.
  • Asynchronous Reset: Clears all internal state and outputs immediately upon reset assertion.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low asynchronous reset
enInput1Enable signal for pulse generation
clrInput1Synchronous clear for sticky flag and counter
winInput4Window width in clock cycles (0-15)
in_pulseInput1Input signal for edge detection
out_pulseOutput1Generated output pulse
sticky_flagOutput1Latched pulse activity flag

Verification

The testbench validates seven key scenarios to ensure robust operation:

  1. Basic Positive Edge: Detects positive edge within window.
  2. Basic Negative Edge: Detects negative edge within window.
  3. Zero Window: Pulse generation is suppressed if win is 0.
  4. Sticky Set: sticky_flag sets correctly upon pulse generation.
  5. Sticky Clear: sticky_flag clears correctly upon clr assertion.
  6. Enable Gating: Pulses are suppressed when en is low.
  7. Reset Behavior: All outputs initialize to zero on rst_n deassertion.

More in Edge, Debounce & Pulse

All Edge, Debounce & Pulse blocks