Edge, Debounce & Pulse

Level-Change Sticky Flag — L1 Upgrade — L2 Upgrade

Module that detects level changes on a single bit, sets a persistent sticky flag, and activates a programmable window timer on each change.

Open in IDE Category Wiki · edge / FF

About this block

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Level-Change Sticky Flag — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a level-change sticky flag with a programmable clear window. It detects rising or falling edges on a single-bit input signal. The sticky flag remains set until explicitly cleared by the clear_sticky signal. A programmable window timer activates on each detected change. The window duration is defined by the window_width input. The window timer is controlled by the window_en enable signal.

This IP provides a robust mechanism for tracking level changes with a configurable observation window. It is suitable for event logging, glitch filtering, or state synchronization interfaces. The design is fully synchronous except for the asynchronous clear and reset. Simulation results confirm correct behavior across all specified scenarios.

Choose Open in IDE. RTL Studio loads the packaged workspace for Level-Change Sticky Flag — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Module that detects level changes on a single bit, sets a persistent sticky flag, and activates a programmable window timer on each change.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The module uses a latch-free design for level change detection. It compares the current input level with the previous clock cycle value. A dedicated register holds the sticky state until reset or clear. The window timer counts down from the configured width. The timer resets automatically when clear_sticky is asserted. The window_active output indicates when the timer is running.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`level_in`	Input	1	Signal to monitor for level changes
`clear_sticky`	Input	1	Asynchronous clear for sticky flag and window
`window_width`	Input	8	Number of cycles for the active window
`window_en`	Input	1	Enable signal for the window timer
`sticky_flag`	Output	1	Persistent flag set on level change
`window_active`	Output	1	High while window timer is counting

Verification

The testbench validates reset behavior, edge detection, and window timing. All seven test cases pass successfully in the Icarus Verilog simulation.

Reset initializes both outputs to zero.
Level changes set the sticky flag immediately.
The window timer activates for the specified number of cycles.
The sticky flag persists after the window expires.
Clearing the sticky flag resets both the flag and the window.
Disabling window_en prevents the timer from starting.
Falling edges are detected with the same logic as rising edges.
Changing window_width correctly adjusts the timer duration.

Test Case	Description	Result
TC1	Reset state check	PASS
TC2	Rising edge detection	PASS
TC3	Window active and expiry	PASS
TC4	Clear sticky flag	PASS
TC5	Window disabled	PASS
TC6	Falling edge detection	PASS
TC7	Window width parameterization	PASS

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