Edge, Debounce & Pulse

Level-to-Pulse Enable — L1 Upgrade — L2 Upgrade

Converts a level signal to a pulse with a configurable hold window and sticky edge flag.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

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Level-to-Pulse Enable — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core converts a continuous level signal into a pulse with a configurable hold window.

It detects both rising and falling edges on the input signal to trigger the pulse output.

A sticky flag latches the occurrence of any edge until explicitly cleared.

Choose Open in IDE. RTL Studio loads the packaged workspace for Level-to-Pulse Enable — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Converts a level signal to a pulse with a configurable hold window and sticky edge flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Edge Detection: Detects both rising and falling edges on the input level signal.
Configurable Hold Window: Generates a pulse output that stays high for a configurable number of clock cycles (WINDOW_WIDTH).
Sticky Flag: The sticky_flag output remains set after any edge event until cleared via clr_sticky.
Window Extension: New edges detected while the window is active reset the counter, extending the pulse duration.
Control Signals: Supports synchronous enable (en) and active-low asynchronous reset (rst_n).

Ports

Port Name	Direction	Width	Description
`clk`	input	1	Clock input
`rst_n`	input	1	Active-low asynchronous reset
`en`	input	1	Synchronous enable
`clr_sticky`	input	1	Synchronous clear for sticky flag
`level_in`	input	1	Input level signal
`pulse_out`	output	1	Pulse output during window
`sticky_flag`	output	1	Latched edge indicator

Parameters

Parameter	Default	Description
`WINDOW_WIDTH`	4	Number of clock cycles the pulse remains high after an edge detection.

Verification

The testbench verifies the following behaviors:

Reset Behavior: Ensures all outputs and internal states are initialized correctly.
Edge Detection: Confirms detection of both rising and falling edges.
Window Logic: Validates that the pulse remains high for the configured window width.
Window Extension: Checks that new edges reset the window counter and extend the pulse.
Sticky Flag: Verifies that the flag latches on any edge and clears only on clr_sticky.
Enable Control: Ensures operations are suspended when en is low.

### Test Cases

Test Case	Description	Result
TC1	Reset Check	PASS
TC2	Basic Rise Edge Detection	PASS
TC3	Fall Edge Detection	PASS
TC4	Sticky Flag Clear	PASS
TC5	Hold Both Edges	PASS
TC6	Disable Behavior	PASS
TC7	Window Reset on New Edge	PASS

All test cases passed successfully in the Icarus Verilog simulation environment.

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