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Edge, Debounce & Pulse

Configurable Minimum Pulse Stretcher

Ensures output pulse width is at least min_width cycles using synchronous reset and single clock domain.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Configurable Minimum Pulse Stretcher is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core ensures that output pulses are at least a configurable minimum width (min_width) cycles.

It is designed for synchronous reset and single clock domain operation.

The module is ideal for debouncing applications or enforcing minimum signal width requirements in digital systems.

  • Configurable Minimum Width: Set via an 8-bit input port.
  • Synchronous Reset: Clean reset behavior on rst_n.
  • Dynamic Reconfiguration: min_width can be changed while the module is active.
  • Verified: Comprehensive testbench covering edge cases including short, long, exact, and dynamic width pulses.
  1. Choose Open in IDE. RTL Studio loads the packaged workspace for Configurable Minimum Pulse Stretcher.
  2. Read the Verilog module in the editor. The catalog line for this block: Ensures output pulse width is at least min_width cycles using synchronous reset and single clock domain.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port NameDirectionWidthDescription
clkInput1Clock input
rst_nInput1Active-low synchronous reset
pulse_inInput1Input pulse signal
min_widthInput8Minimum output pulse width in cycles (0-255)
pulse_outOutput1Stretched output pulse

Architecture

The design uses a counter and a detection flag to manage pulse stretching logic.

### Logic Flow

  1. Idle State: Output is low. Counter is zero.
  2. Pulse Detected: When pulse_in goes high, pulse_detected is set, and the counter starts incrementing. Output is driven high.
  3. Pulse Ends: When pulse_in goes low, the module checks if the counter value is less than min_width.

- If cnt < min_width: The output remains high, and the counter continues to increment until cnt == min_width. - If cnt >= min_width: The output goes low immediately, and the state returns to idle.

Verification

The provided testbench (tb_pulse_stretcher_min_width.v) validates the following scenarios:

Test CaseDescriptionExpected Result
TC1Short pulse (1 cycle) with min_width 4Output stretched to 4 cycles
TC2Long pulse (10 cycles) with min_width 4Output follows input
TC3Exact width pulse (4 cycles) with min_width 4Output matches input
TC4Dynamic min_width changeOutput adapts to new width

### Running Simulation

After running the simulation, the Log panel should display:

  • TC1 PASS - Short pulse stretched correctly
  • TC2 PASS - Long pulse followed correctly
  • TC3 PASS - Exact width pulse handled correctly
  • TC4 PASS - Dynamic min width handled correctly
  • INFO: PASS

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