Edge, Debounce & Pulse

Rising-Edge Hold for N Cycles — L1 Upgrade — L2 Upgrade

Rising-Edge Hold for N Cycles with configurable window and sticky rearm capability.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

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Rising-Edge Hold for N Cycles — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements a robust rising-edge detection mechanism with a configurable hold period and an optional rearm window. It asserts pulse_out for a specified number of cycles after detecting a rising edge on the re input. After the hold period expires, it can optionally enter a window state to detect re-assertion or simply remain low. This design is suitable for debouncing, pulse stretching, or event windowing in digital systems.

The module is fully verified, synthesizable, and ready for integration into larger designs.

This IP core provides a reliable solution for detecting rising edges with customizable pulse width and rearm window capabilities. It is designed for easy integration, featuring synchronous clear and asynchronous reset controls. The included testbench ensures robust verification of all functional modes, making it a safe and effective component for digital system designs requiring precise timing control.

Choose Open in IDE. RTL Studio loads the packaged workspace for Rising-Edge Hold for N Cycles — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Rising-Edge Hold for N Cycles with configurable window and sticky rearm capability.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Rising Edge Detection: Detects the rising edge of the re signal using edge detection logic.
Configurable Hold Duration: Sets the number of cycles pulse_out remains high via the hold_n parameter (0-15 cycles).
Configurable Rearm Window: Optional window period after hold expires to detect re-triggering, set via window_n (0-15 cycles).
Reset & Clear:

- Asynchronous active-low reset (rst_n). - Synchronous active-high clear (clear).

4-bit Counter Width: Supports hold and window durations from 0 to 15 cycles.

Interface

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`re`	Input	1	Rising-edge trigger signal
`clear`	Input	1	Active-high synchronous clear
`hold_n`	Input	4	Number of cycles to hold pulse high
`window_n`	Input	4	Number of cycles for the rearm window
`pulse_out`	Output	1	Output pulse signal

Architecture

The module uses a state machine to manage the hold and window phases. It detects a rising edge on re by comparing the current and previous clock cycles. Upon detection, it enters the hold state and counts down hold_n. Once the hold counter reaches zero, it transitions to the window state if window_n is non-zero. During the window state, it counts down window_n. The clear signal forces an immediate reset of all internal states. The rst_n signal resets all registers asynchronously.

Verification

The testbench verifies basic hold functionality, window functionality after the hold period, synchronous clear signal, and asynchronous reset signal. All test cases passed successfully.

Test Case	Description	Result
TC1	Basic hold functionality	PASS
TC2	Window functionality	PASS
TC3	Clear functionality	PASS
TC4	Reset functionality	PASS

To run the simulation:

Use RtlStudio Waveform tab with sim/dump.vcd for detailed signal analysis.
Check the Log panel for INFO: PASS upon completion.

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