Edge, Debounce & Pulse

Pulse Gap Detector 8-bit

Detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold.

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About this block

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Pulse Gap Detector 8-bit is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold. It is designed for applications requiring signal continuity monitoring, such as heartbeat detection or communication link integrity checks.

The module uses a synchronous 8-bit counter to measure the gap in clock cycles. When the counter value exceeds the configured threshold, the gap_too_long output is asserted high. This provides a simple and efficient solution for gap detection in digital systems.

Choose Open in IDE. RTL Studio loads the packaged workspace for Pulse Gap Detector 8-bit.
Read the Verilog module in the editor. The catalog line for this block: Detects if the time interval between consecutive input pulses exceeds a configurable 8-bit threshold.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Threshold: 8-bit input port allows flexible gap threshold configuration (0-255 cycles).
Continuous Monitoring: Real-time detection of pulse gaps via continuous comparator logic.
Asynchronous Reset: Ensures clean initialization state via rst_n.
Synchronous Logic: Easy integration into synchronous digital systems.
Output Flag: Asserts gap_too_long when the gap exceeds the threshold.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`pulse_in`	Input	1	Input pulse signal (rising edge triggers counter reset)
`threshold`	Input	7:0	Gap threshold value (8-bit)
`gap_too_long`	Output	1	High when gap exceeds threshold

Architecture

The module counts clock cycles between rising edges of the pulse_in signal. The logic operates as follows:

Counter: An 8-bit counter increments on each clock cycle.
Edge Detection: A rising edge on pulse_in resets the counter to zero.
Comparison: The current counter value is continuously compared against the threshold.
Output: gap_too_long is asserted high if counter > threshold.

Verification

The testbench verifies three key scenarios:

Test Case	Description	Expected Result
TC1	Short Gap (5 cycles, Threshold 10)	`gap_too_long` remains low
TC2	Long Gap (15 cycles, Threshold 10)	`gap_too_long` goes high
TC3	Exact Threshold (10 cycles, Threshold 10)	`gap_too_long` remains low

All tests passed successfully in the Icarus Verilog simulation environment.

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