Edge, Debounce & Pulse

Double-Pulse Rejector

Passes first pulse, rejects subsequent pulses within N cycles.

Open in IDE Category Wiki · edge / FF

About this block

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Double-Pulse Rejector is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

The Double-Pulse Rejector is a Verilog module that filters input pulse trains. It passes the first pulse of a sequence and rejects subsequent pulses within a configurable refractory period. This IP is useful for debouncing sensors or preventing rapid trigger events.

This IP provides a robust solution for double-pulse rejection. It is easy to integrate and configure via the N parameter. The design is fully verified with a standard testbench.

Choose Open in IDE. RTL Studio loads the packaged workspace for Double-Pulse Rejector.
Read the Verilog module in the editor. The catalog line for this block: Passes first pulse, rejects subsequent pulses within N cycles.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Passes the initial rising edge of an input pulse.
Rejects any additional pulses occurring within N clock cycles.
Configurable refractory period via the N parameter.
Synchronous reset with active-low polarity.
Simple synchronous state machine implementation.
Includes a comprehensive testbench with four verification cases.

Ports

Port Name	Direction	Width	Description
clk	Input	1	Clock input.
rst_n	Input	1	Active-low synchronous reset.
pulse_in	Input	1	Input pulse signal.
pulse_out	Output	1	Output pulse signal.

Architecture

The module uses a two-state finite state machine to manage pulse detection. The states are IDLE and ACTIVE (refractory). A 32-bit counter tracks the remaining cycles in the refractory period. Rising edge detection is performed using a two-stage flip-flop chain.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Single pulse input	pulse_out is high for one cycle.
TC2	Double pulse input	First pulse passed, second rejected.
TC3	Pulse after refractory	Pulse passed after N cycles.
TC4	Three spaced pulses	All three pulses passed.

All test cases passed successfully in the simulation log.

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