Edge, Debounce & Pulse

Quadrature Decoder x4 — L2 Upgrade

Quadrature Decoder x4 with windowed sticky inactivity flag.

Open in IDE Category Wiki · edge / FF

About this block

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Quadrature Decoder x4 — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP implements a high-performance quadrature decoder with x4 frequency multiplication. It accurately detects rotation direction (CW/CCW) from standard A/B phase inputs and includes a configurable windowed inactivity detector to identify when the encoder has stopped moving.

The design is synchronous, robust against noise via double-registering, and suitable for L2 integration in embedded systems.

This IP provides a robust, synchronous quadrature decoder with x4 resolution and inactivity detection. It is designed for easy integration into L2 systems, featuring metastability protection and configurable timeout thresholds. The included testbench ensures reliable operation for both CW and CCW rotation detection, as well as proper handling of inactivity flags and system resets.

Choose Open in IDE. RTL Studio loads the packaged workspace for Quadrature Decoder x4 — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: Quadrature Decoder x4 with windowed sticky inactivity flag.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

x4 Resolution: Detects transitions on all edges of A and B phases.
Direction Detection: Identifies Clockwise (CW) and Counter-Clockwise (CCW) rotation.
Inactivity Detection: Configurable window counter to detect stationary encoders.
Sticky Flag: Maintains inactivity status until explicitly cleared.
Metastability Protection: Double-registering of inputs.

Architecture

Input Synchronization: The a_b inputs are registered twice (a_b_d1, a_b_d2) to mitigate metastability and ensure clean edge detection.
Transition Detection: The logic compares the current state with the previous state to identify valid quadrature transitions.
Direction Logic: Based on the Gray code sequence of transitions, the direction (dir) is determined:

* 1'b1: Clockwise (CW) * 1'b0: Counter-Clockwise (CCW)

Window Counter: A counter increments on every clock cycle where no valid transition is detected. It resets to zero on any valid transition.
Sticky Flag: When the window counter reaches the window_cnt threshold, window_expired is set, which asserts sticky_flag. The flag remains set until explicitly cleared.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low asynchronous reset
`a_b`	Input	2	Quadrature A/B inputs
`clear_sticky`	Input	1	Active-high clear for sticky flag
`window_cnt`	Input	8	Window counter threshold (0-255)
`dir`	Output	1	Detected direction (1=CW, 0=CCW)
`sticky_flag`	Output	1	Inactivity flag (sticky)

Verification

The testbench verifies five key scenarios:

TC1: Basic CW rotation detection.
TC2: Basic CCW rotation detection.
TC3: Window expiry setting the sticky flag.
TC4: Clearing the sticky flag.
TC5: System reset functionality.

All tests passed successfully in simulation.

Test Case	Description	Result
TC1	Basic CW rotation	PASS
TC2	Basic CCW rotation	PASS
TC3	Window sticky flag	PASS
TC4	Clear sticky flag	PASS
TC5	Reset functionality	PASS

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