Edge, Debounce & Pulse

Min-Width Pulse Filter N

Filters input pulses to ensure they meet a minimum width of N clock cycles.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

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Min-Width Pulse Filter N is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This module filters input pulses to ensure they meet a minimum width of N clock cycles. Pulses shorter than N cycles are rejected and produce a low output. Pulses equal to or longer than N cycles are passed through to the output. The output is registered to avoid glitches and ensure clean timing.

This IP provides a robust solution for filtering short pulses in digital designs.

It is suitable for debouncing or signal validation applications.

Choose Open in IDE. RTL Studio loads the packaged workspace for Min-Width Pulse Filter N.
Read the Verilog module in the editor. The catalog line for this block: Filters input pulses to ensure they meet a minimum width of N clock cycles.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Configurable Minimum Width: The minimum pulse width N is configurable via a 4-bit input port (range 1-15).
Glitch-Free Output: The output is registered to ensure clean timing and avoid metastability or glitches.
Simple FSM: Implemented using a simple Finite State Machine for predictable behavior.
Comprehensive Verification: Includes a testbench with multiple test cases covering edge conditions.

Ports

Port	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`n`	Input	4	Minimum pulse width in cycles [3:0]
`pulse_in`	Input	1	Input pulse signal
`pulse_out`	Output	1	Filtered output pulse

Architecture

The module uses a finite state machine with two primary logical states: IDLE and COUNTING (implicit in the code via the counting register).

IDLE State: The module waits for pulse_in to go high.
COUNTING State: Once pulse_in is high, the counter increments each cycle.

- If pulse_in goes low before the count reaches n, the counter resets, and the output remains low. - If the count reaches n, the output is asserted high. - If pulse_in remains high after reaching n, the output stays high. - If pulse_in goes low after the output has been asserted, the output is de-asserted, and the state returns to IDLE.

Verification

The testbench verifies the following scenarios:

Test Case	Description	Expected Result
TC1	Pulse shorter than N	Rejected
TC2	Pulse exactly N cycles	Accepted
TC3	Pulse longer than N	Accepted
TC4	N=1, pulse=1 cycle	Accepted
TC5	N=1, no pulse	Rejected

### Running the Simulation

Ensure you have a Verilog simulator installed (e.g., Icarus Verilog, ModelSim).
Run the simulation script provided in the repository (e.g., run_sim.sh or similar).
Check the log output for the following expected results:

- TC1 PASS pulse too short - TC2 PASS pulse exactly N - TC2 PASS pulse drop - TC3 PASS pulse > N - TC3 PASS pulse drop - TC4 PASS N=1 pulse=1 - TC4 PASS N=1 drop - TC5 PASS N=1 no pulse - Simulation ends with INFO: PASS.

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