Edge, Debounce & Pulse

8-Bit Sticky OR Accumulator — L1 Upgrade — L2 Upgrade

8-Bit Sticky OR Accumulator with configurable window clear and explicit reset capabilities.

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About this block

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8-Bit Sticky OR Accumulator — L1 Upgrade — L2 Upgrade is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP core implements an 8-bit accumulator with a sticky OR flag and a configurable window-based clear mechanism. It is designed for edge pulse processing applications where non-zero events must be tracked until a specific time window expires or is explicitly cleared.

The module supports synchronous operation with an active-low reset and is suitable for event logging, pulse counting, and periodic reset scenarios.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit Sticky OR Accumulator — L1 Upgrade — L2 Upgrade.
Read the Verilog module in the editor. The catalog line for this block: 8-Bit Sticky OR Accumulator with configurable window clear and explicit reset capabilities.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

8-bit Accumulation: Sums incoming 8-bit data when enabled.
Sticky OR Flag: Sets a flag if any non-zero data is accumulated.
Configurable Window Clear: Automatically clears the sticky flag when a configurable window counter expires.
Explicit Clear: Supports a synchronous clear signal to reset the sticky flag.
Active-Low Reset: Standard synchronous reset behavior for all internal registers.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low reset
`en`	Input	1	Enable signal for accumulation
`data_in`	Input	8	Data input to accumulate
`window_en`	Input	1	Enable signal for the window counter
`window_size`	Input	4	Size of the window counter (0-15)
`clear_sticky`	Input	1	Explicit clear signal for the sticky flag
`acc_out`	Output	8	Accumulator output
`sticky_flag`	Output	1	Sticky OR flag

Verification

### Simulation

Run the provided testbench to verify functionality. The simulation includes the following test cases:

Test Case	Description	Expected Result
TC1	Basic Accumulation	Accumulator sums `data_in` correctly
TC2	Sticky Flag Set	Sticky flag remains set after `data_in` becomes zero
TC3	Window Clear Sticky	Sticky flag clears when window is active
TC4	Explicit Clear Sticky	Sticky flag clears when `clear_sticky` is asserted
TC5	Reset	Accumulator and sticky flag reset to zero

### Expected Output

Upon successful simulation, the log should display:

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