Edge, Debounce & Pulse

Synchronized Debouncer with Edge Detection

A synchronized debouncer that filters noisy input signals and provides clean edge detection pulses.

Open in IDE Category Wiki · edge / FF

About this block

Simulate it in the Verilog IDE

Mediumverilogsimsyn

Synchronized Debouncer with Edge Detection is a Verilog reference block in the Edge, Debounce & Pulse catalog. Edge detectors, debouncers, pulse stretchers, and one-shot generators. Marked Medium: more state or a wider datapath, still one workspace in the IDE.

This IP provides a robust solution for cleaning noisy digital signals. It synchronizes asynchronous inputs to the local clock domain and filters out glitches shorter than a configurable threshold. Additionally, it provides edge detection logic to identify rising and falling transitions on the clean signal.

This IP effectively mitigates switch bounce and noise in digital systems. The synchronized design ensures safe integration into synchronous logic. Engineers can tune the debounce count to balance latency and noise immunity. Edge detection provides convenient triggers for state machines without additional logic.

Choose Open in IDE. RTL Studio loads the packaged workspace for Synchronized Debouncer with Edge Detection.
Read the Verilog module in the editor. The catalog line for this block: A synchronized debouncer that filters noisy input signals and provides clean edge detection pulses.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

Metastability Protection: Two-stage synchronizer prevents metastability propagation from asynchronous inputs.
Configurable Debounce: Adjustable debounce time via the DEBOUNCE_COUNT parameter.
Edge Detection: Dedicated pos_edge and neg_edge pulse outputs for rising and falling transitions.
Synchronous Reset: All internal states are reset synchronously.
Verified: Tested with Icarus Verilog simulation.

Ports

Port Name	Direction	Width	Description
`clk`	Input	1	Clock input
`rst_n`	Input	1	Active-low synchronous reset
`raw_in`	Input	1	Asynchronous or noisy input signal
`deb_out`	Output	1	Cleaned, debounced output signal
`pos_edge`	Output	1	High for one cycle on rising edge
`neg_edge`	Output	1	High for one cycle on falling edge

Architecture

The design follows a three-stage pipeline:

Synchronization: Aligns raw_in with clk using two flip-flops.
Debouncing: Counts consecutive stable cycles of the synchronized signal.
Edge Detection: Identifies transitions on the debounced state.

Parameters

Parameter	Default	Description
`DEBOUNCE_COUNT`	1000	Number of clock cycles required for stability before updating state

Verification

The testbench validates reset behavior, signal stability, edge detection, and glitch rejection.

Test Case	Description	Result
TC1	Reset forces outputs to zero	PASS
TC2	Stable high input results in high output	PASS
TC3	Falling edge detection and state change	PASS
TC4	Rising edge detection and state change	PASS
TC5	Glitch rejection for short pulses	PASS
TC6	Metastability resilience check	PASS

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