Logic Gates

2-Input AND Gate

A basic 2-input AND gate implemented in Verilog.

Open in IDE Category Wiki · gates

About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

2-Input AND Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

An OpenIP implementation of a basic 2-input AND gate written in Verilog. This module is designed for digital logic synthesis and simulation workflows.

This component provides a standard 2-input AND gate for digital logic designs. It is suitable for basic logic synthesis and simulation workflows.

The module performs a logical AND operation on two single-bit inputs. It produces a single-bit output that is high only when both inputs are high.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Input AND Gate.
Read the Verilog module in the editor. The catalog line for this block: A basic 2-input AND gate implemented in Verilog.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
a	input	1	First input bit
b	input	1	Second input bit
y	output	1	Logical AND result

Verification

The testbench covers all four combinations of the truth table.

Test Case	Input a	Input b	Expected y	Result
TC1	0	0	0	PASS
TC2	0	1	0	PASS
TC3	1	0	0	PASS
TC4	1	1	1	PASS

All simulation tests passed successfully.

More in Logic Gates

All Logic Gates blocks