Logic Gates
2-Input OR Gate
A basic 2-input OR gate implemented in Verilog for digital logic design.
About this block
Simulate it in the Verilog IDE
2-Input OR Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This OpenIP provides a simple, verified 2-input OR gate implemented in Verilog. It is designed for educational purposes and as a basic building block for larger digital logic designs. The module is fully combinational, requires no clocking, and has been verified against all four possible input combinations.
The or_gate_2input module performs a logical OR operation on two single-bit inputs (a and b) and produces a single-bit output (y). It is lightweight, stateless, and suitable for integration into any digital system requiring basic boolean logic.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Input OR Gate.
- Read the Verilog module in the editor. The catalog line for this block: A basic 2-input OR gate implemented in Verilog for digital logic design.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The design consists of a single Verilog module with no internal state or clocking requirements. The logic is implemented using a continuous assignment, ensuring minimal latency and resource usage.
Interface
The module exposes the following ports:
| Port | Direction | Width | Description |
|---|---|---|---|
| a | Input | 1 | First input bit |
| b | Input | 1 | Second input bit |
| y | Output | 1 | Logical OR result |
Verification
The design has been verified using a self-checking testbench that applies all four input combinations. The simulation is performed using Icarus Verilog.
### Test Results
| Test Case | a | b | Expected y | Result |
|---|---|---|---|---|
| TC1 | 0 | 0 | 0 | PASS |
| TC2 | 0 | 1 | 1 | PASS |
| TC3 | 1 | 0 | 1 | PASS |
| TC4 | 1 | 1 | 1 | PASS |
All test cases passed successfully. The simulation log confirms correct logical behavior with the final output:
More in Logic Gates
- 2-Input AND Gate
- 2-Input NAND Gate
- 2-Input NOR Gate
- 2-Input XOR Gate
- 3-Input Bitwise NOR Gate
- 3-Input Majority Voter
- 3-State Buffer with Enable and High-Z
- 5-Input Majority Voter with Fault Tolerance
- 8-Bit Bitwise XNOR Gate
- 8-Bit NAND Reduction
- 8-Input Majority Voter
- Bitwise Mask AND/OR 8-bit
- OR-Reduce 8-Bit
- Priority Mask-Below 8-bit
- XOR-Reduce Tree 8-bit