Logic Gates
8-Bit NAND Reduction
Computes the NAND of all bits in an 8-bit input vector.
About this block
Simulate it in the Verilog IDE
8-Bit NAND Reduction is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements an 8-bit NAND reduction gate. It computes the NAND of all bits in an 8-bit input vector. The output is low only when all input bits are high.
This IP provides a simple and efficient 8-bit NAND reduction. It is suitable for control logic and parity-like checks. The design is fully combinational with zero latency.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Bit NAND Reduction.
- Read the Verilog module in the editor. The catalog line for this block: Computes the NAND of all bits in an 8-bit input vector.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The design uses a single continuous assignment statement. It reduces the 8-bit input using the bitwise AND operator. The result is inverted to produce the NAND output.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
| data | Input | [7:0] | Input data vector |
| y | Output | 1 | NAND reduction result |
Verification
The testbench verifies three specific scenarios. Test Case 1 checks the all-ones input condition. Test Case 2 checks the all-zeros input condition. Test Case 3 checks a mixed-bit input condition. All test cases passed successfully in simulation.
| Test Case | Input | Expected Output | Status |
|---|---|---|---|
| TC1 | 8'hFF | 1'b0 | PASS |
| TC2 | 8'h00 | 1'b1 | PASS |
| TC3 | 8'hAB | 1'b1 | PASS |
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- 3-Input Majority Voter
- 3-State Buffer with Enable and High-Z
- 5-Input Majority Voter with Fault Tolerance
- 8-Bit Bitwise XNOR Gate
- 8-Input Majority Voter
- Bitwise Mask AND/OR 8-bit
- OR-Reduce 8-Bit
- Priority Mask-Below 8-bit
- XOR-Reduce Tree 8-bit