Logic Gates

8-Input Majority Voter

Combinational logic that outputs high when 5 or more of 8 inputs are high.

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About this block

Simulate it in the Verilog IDE

Easyverilogsimsyn

8-Input Majority Voter is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP implements an 8-input majority voter.

The output is high when five or more inputs are logic one.

It uses a population count approach for verification.

Choose Open in IDE. RTL Studio loads the packaged workspace for 8-Input Majority Voter.
Read the Verilog module in the editor. The catalog line for this block: Combinational logic that outputs high when 5 or more of 8 inputs are high.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Architecture

The design sums all eight input bits.

The result is compared against the threshold of five.

The output drives high if the count meets or exceeds five.

Ports

Port	Direction	Width	Description
in	Input	[7:0]	Input vector
y	Output	1	Majority result

Verification

The testbench covers ten specific test cases.

It checks boundary conditions for counts zero through eight.

It also verifies random bit patterns.

All tests passed successfully in simulation.

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