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Logic Gates

3-Input Bitwise NOR Gate

A configurable-width combinational module that performs a bitwise NOR operation on three input vectors.

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About this block

Simulate it in the Verilog IDE

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3-Input Bitwise NOR Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP core implements a combinational 3-input bitwise NOR gate. It accepts three parallel data vectors (din_a, din_b, din_c) and produces a single output vector (dout) representing the bitwise NOR of the inputs.

The design is fully parameterizable via the WIDTH parameter, allowing for flexible integration into various data paths and control logic. It is pure combinational logic, meaning it has no clock dependency, making it suitable for asynchronous paths or synchronous designs with registered inputs/outputs.

  1. Choose Open in IDE. RTL Studio loads the packaged workspace for 3-Input Bitwise NOR Gate.
  2. Read the Verilog module in the editor. The catalog line for this block: A configurable-width combinational module that performs a bitwise NOR operation on three input vectors.
  3. Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
  4. Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Features

  • Configurable Width: Supports any bit width via the WIDTH parameter (default: 8).
  • Pure Combinational Logic: No clock dependency; suitable for asynchronous paths or synchronous designs with registered inputs/outputs.
  • Verified: Rigorously tested against truth tables and random stimulus vectors.
  • Lightweight: Minimal resource usage, ideal for control logic or data manipulation.

Ports

Port NameDirectionWidthDescription
din_aInputWIDTHFirst input vector
din_bInputWIDTHSecond input vector
din_cInputWIDTHThird input vector
doutOutputWIDTHResult of `~(din_adin_bdin_c)`

Verification

The testbench (tb/tb_bitwise_nor_3input.v) covers the following scenarios:

Test CaseDescriptionExpected Result
TC1All inputs zeroOutput all ones
TC2All inputs oneOutput all zeros
TC3Mixed inputs (one all-ones vector)Output all zeros
TC4100 Random vectorsOutput matches `~(abc)`
TC5Single bit set in one inputOutput correctly inverted

All tests pass successfully upon simulation. Expected output includes:

  • INFO: TC1 PASS (All 0 input -> All 1 output)
  • INFO: TC2 PASS (All 1 input -> All 0 output)
  • INFO: TC3 PASS (Mixed inputs with one all-1 -> 0 output)
  • INFO: TC4 PASS (100 Random vectors)
  • INFO: TC5 PASS (Single bit set -> Inverted result)
  • INFO: PASS

Constraints

  • Timing: As a combinational block, propagation delay depends on the WIDTH and target technology. For high-speed designs, consider registering inputs and outputs.
  • Area: Resource usage scales linearly with WIDTH. For large widths, ensure the target FPGA/ASIC has sufficient logic resources.

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