Logic Gates
5-Input Majority Voter with Fault Tolerance
Combinational 5-input majority voter with a tie flag for boundary cases.
About this block
Simulate it in the Verilog IDE
5-Input Majority Voter with Fault Tolerance is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP implements a combinational 5-input majority voter. It outputs a high signal when three or more inputs are logic high. It includes a fault-tolerance flag (tie) for ambiguous boundary cases (sums of 2 or 3). The design uses a simple population count adder tree, ensuring high synthesizability, low latency, and clarity.
This IP provides a robust, fully synthesizable 5-input majority voter with an additional "tie" flag for boundary detection. It is suitable for voting-based redundancy systems where fault tolerance or error detection is required.
- Choose Open in IDE. RTL Studio loads the packaged workspace for 5-Input Majority Voter with Fault Tolerance.
- Read the Verilog module in the editor. The catalog line for this block: Combinational 5-input majority voter with a tie flag for boundary cases.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Features
- 5-bit Parallel Input: Accepts a 5-bit input vector.
- Majority Output: Single-bit output asserted when >= 3 inputs are high.
- Tie Flag: Single-bit output asserted when the sum of inputs is exactly 2 or 3 (boundary cases).
- Combinational Logic: Pure combinational implementation for minimal latency.
- Verified: Comprehensive testbench covering all population count scenarios (0-5) and random permutations.
Ports
| Port | Direction | Width | Description |
|---|---|---|---|
in | Input | [4:0] | 5-bit input vector |
out | Output | 1 | Majority output (1 if >= 3 inputs are 1) |
tie | Output | 1 | Tie/ambiguous flag (1 if exactly 2 or 3 inputs are 1) |
Architecture
The module calculates the sum of all input bits using a continuous assignment adder tree. The sum ranges from 0 to 5 and fits in 3 bits.
- Majority Output: Asserted when
sum >= 3. - Tie Flag: Asserted when
sum == 2orsum == 3. This identifies boundary cases where a single bit flip changes the majority result.
Verification
The testbench covers all population count scenarios (sums 0-5) and verifies random permutations for sum=3. All test cases passed in the simulation log.
| Test Case | Input Sum | Expected out | Expected tie | Result |
|---|---|---|---|---|
| TC1 | 0 | 0 | 0 | PASS |
| TC2 | 1 | 0 | 0 | PASS |
| TC3 | 2 | 0 | 1 | PASS |
| TC4 | 3 | 1 | 1 | PASS |
| TC5 | 4 | 1 | 0 | PASS |
| TC6 | 5 | 1 | 0 | PASS |
| TC7 | 3 | 1 | 1 | PASS |
More in Logic Gates
- 2-Input AND Gate
- 2-Input NAND Gate
- 2-Input NOR Gate
- 2-Input OR Gate
- 2-Input XOR Gate
- 3-Input Bitwise NOR Gate
- 3-Input Majority Voter
- 3-State Buffer with Enable and High-Z
- 8-Bit Bitwise XNOR Gate
- 8-Bit NAND Reduction
- 8-Input Majority Voter
- Bitwise Mask AND/OR 8-bit
- OR-Reduce 8-Bit
- Priority Mask-Below 8-bit
- XOR-Reduce Tree 8-bit