Logic Gates
Priority Mask-Below 8-bit
Generates a mask of all bits strictly below the highest set bit in an 8-bit request vector.
About this block
Simulate it in the Verilog IDE
Priority Mask-Below 8-bit is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.
This IP generates a priority mask based on the highest set bit in an 8-bit request vector. All bits strictly below the highest set bit are asserted in the mask output. If the request vector is zero, the mask output is also zero.
This IP provides a simple combinational priority mask generator. It is suitable for interrupt controllers or arbitration logic. The implementation is efficient and fully verified.
- Choose Open in IDE. RTL Studio loads the packaged workspace for Priority Mask-Below 8-bit.
- Read the Verilog module in the editor. The catalog line for this block: Generates a mask of all bits strictly below the highest set bit in an 8-bit request vector.
- Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
- Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.
RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.
Architecture
The module uses a combinational priority encoder structure. It checks bits from most significant to least significant. The mask is constructed using conditional assignments.
Interface
| Port | Direction | Width | Description |
|---|---|---|---|
| req | Input | 8 | Request vector |
| mask | Output | 8 | Priority mask below highest bit |
Verification
The testbench verifies single-bit requests and multi-bit requests. It confirms that the mask reflects all bits below the highest set bit. It also checks the edge case where the request is zero.
| Test Case | Description | Expected Result |
|---|---|---|
| TC1a | req=0x01 (bit 0) | mask=0x00 |
| TC1b | req=0x02 (bit 1) | mask=0x01 |
| TC1c | req=0x04 (bit 2) | mask=0x03 |
| TC1d | req=0x80 (bit 7) | mask=0x7F |
| TC2a | req=0x03 (bits 0,1) | mask=0x01 |
| TC2b | req=0x07 (bits 0,1,2) | mask=0x03 |
| TC2c | req=0xFF (all bits) | mask=0x7F |
| TC2d | req=0x81 (bits 0,7) | mask=0x7F |
| TC3a | req=0x00 (zero) | mask=0x00 |
All tests passed successfully. Simulation was performed using Icarus Verilog.
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