Logic Gates

2-Input XOR Gate

Basic 2-input XOR logic gate implementation in Verilog.

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About this block

Simulate it in the Verilog IDE

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2-Input XOR Gate is a Verilog reference block in the Logic Gates catalog. AND, OR, XOR, and other combinational gate and boolean logic primitives. Marked Easy: a small block you can read, simulate, and synthesize in one sitting.

This IP provides a minimal, synthesizable 2-input XOR gate implemented in Verilog. It is designed for educational purposes and simple logic manipulation tasks. The design is fully verified with a testbench covering all input combinations and is compatible with standard Verilog simulators (VCS, Icarus Verilog) and synthesis tools.

The module performs an exclusive-OR operation on two single-bit inputs (a and b). The output y is high (1) only when the inputs differ, and low (0) when they are the same. The implementation is purely combinational with no clock dependency.

Choose Open in IDE. RTL Studio loads the packaged workspace for 2-Input XOR Gate.
Read the Verilog module in the editor. The catalog line for this block: Basic 2-input XOR logic gate implementation in Verilog.
Run the packaged testbench with the in-browser Verilator simulator, then open the VCD in the waveform viewer.
Run Yosys in the same IDE for a generic netlist. Sky130 liberty mapping is a separate Pro library option.

RTL Studio is the Verilog simulator and IDE around this block: Slang lint, Verilator, VCD waveforms, and Yosys, in the browser. Simulation guide · Yosys guide.

Ports

Port	Direction	Width	Description
a	input	1	First input bit
b	input	1	Second input bit
y	output	1	XOR result

Verification

The testbench (tb/tb_xor_gate_2input.v) covers all four input combinations to verify correctness.

Test Case	Input a	Input b	Expected y	Result
TC1	0	0	0	PASS
TC2	0	1	1	PASS
TC3	1	0	1	PASS
TC4	1	1	0	PASS

All tests passed successfully. Use the VCD dump to inspect signals.

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